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b=GmV6YtfTTPBMdsdlmzC22knAQSwq3cJCYV26+qTliwttDzbiF2kk+NOzFTtHe5oE4V XrhiZeVAhUFxHELcuytpWo6t9NVeU5j7tIEwL979UPJWPB7nXfK8YvhuAdgL0D5SsrUq xyhrh+nmQGRlJKFwmeLSfvwIafLzRyLosmbNgs0uQlrk+nqriRrp3PF5StwU8C/kz2NA 3wvBrSKN0ieUG6K/T83wj+gxHYKFjJd6r4ETnlrzwQyvLamCnTW179tEgn5BRAox15CB dn/IUfUJUBjsEKJUhNcO1nGT3iyaKgun4DPs6eQ/gUmJA1fepO6FDnmQkq/p/7j9wojT touQ== X-Forwarded-Encrypted: i=1; AJvYcCVxQbmEnytL6nKKlzMVl8j6Ii8ceTvUj8WBWuACWXqIYR10j0F1y38Zu50yoRlHHecgUiq9/U6HVTsNhQYNPRF4GRU5 X-Gm-Message-State: AOJu0YwTrBlrocVQ8kL5in8G8POwWvZ2sIdSNCr0l5uk6IJMcBieQkRq k/IortKtC0ezEUekbMxhgROdqvfNpGT/DC+qaWb0AhgFnHRmWw+sSXyKT5c66kIvDNfm7ZPdCXq oRC3ZXQ== X-Google-Smtp-Source: AGHT+IGmigk3vBnW7SnpRMwSoZkgDc4bh9EamVvfQF1uS77a7Lmp6JCTvus9kRCVQsScSgZ+HIaoTD+fJiMu X-Received: from mizhang-super.c.googlers.com ([35.247.89.60]) (user=mizhang job=sendgmr) by 2002:a05:6a02:592:b0:5dc:6127:e8b6 with SMTP id by18-20020a056a02059200b005dc6127e8b6mr24957pgb.3.1714973478215; Sun, 05 May 2024 22:31:18 -0700 (PDT) Reply-To: Mingwei Zhang Date: Mon, 6 May 2024 05:29:52 +0000 In-Reply-To: <20240506053020.3911940-1-mizhang@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240506053020.3911940-1-mizhang@google.com> X-Mailer: git-send-email 2.45.0.rc1.225.g2a3ae87e7f-goog Message-ID: <20240506053020.3911940-28-mizhang@google.com> Subject: [PATCH v2 27/54] KVM: x86/pmu: Exclude PMU MSRs in vmx_get_passthrough_msr_slot() From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , Mingwei Zhang , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , maobibo , Like Xu , Peter Zijlstra , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org Reject PMU MSRs interception explicitly in vmx_get_passthrough_msr_slot() since interception of PMU MSRs are specially handled in intel_passthrough_pmu_msrs(). Signed-off-by: Mingwei Zhang Signed-off-by: Dapeng Mi --- arch/x86/kvm/vmx/vmx.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index c9de7d2623b8..62b5913abdd6 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -164,7 +164,7 @@ module_param(enable_passthrough_pmu, bool, 0444); /* * List of MSRs that can be directly passed to the guest. - * In addition to these x2apic, PT and LBR MSRs are handled specially. + * In addition to these x2apic, PMU, PT and LBR MSRs are handled specially. */ static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = { MSR_IA32_SPEC_CTRL, @@ -694,6 +694,13 @@ static int vmx_get_passthrough_msr_slot(u32 msr) case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8: case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8: /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */ + case MSR_IA32_PMC0 ... MSR_IA32_PMC0 + 7: + case MSR_IA32_PERFCTR0 ... MSR_IA32_PERFCTR0 + 7: + case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + 2: + case MSR_CORE_PERF_GLOBAL_STATUS: + case MSR_CORE_PERF_GLOBAL_CTRL: + case MSR_CORE_PERF_GLOBAL_OVF_CTRL: + /* PMU MSRs. These are handled in intel_passthrough_pmu_msrs() */ return -ENOENT; }