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AJvYcCUKPT2sJwXVOntQrpoNhFHRKFFQkMZcB1XMSzW/a0Sv9y833PHDXwpDOet5NERFy5CSx57bubRAKtCVISfAo8qUgtRk X-Gm-Message-State: AOJu0Yyy+8Zt+RxEexBf4w8T6k9gOiI4QFaIhb/GKZqSBvhTf7xS9Fb1 LndivTPrLPaOcCJ4nJ84UMOdUDiCy7DAYo6X1eYxJqg0HUR0XcJvqZtQMXLKjWuXDuPe8mosFXP a75Vhbw== X-Google-Smtp-Source: AGHT+IH/mxinAZrdz3Klst7c4dV90NWXmunIvbcDxzTOCTvEO16RxUWtLqzAlW0j4Xl1ImWkT0Ah5CH55iWI X-Received: from mizhang-super.c.googlers.com ([35.247.89.60]) (user=mizhang job=sendgmr) by 2002:a17:90b:8d6:b0:2b3:5eb5:6a76 with SMTP id ds22-20020a17090b08d600b002b35eb56a76mr25362pjb.3.1714973495401; Sun, 05 May 2024 22:31:35 -0700 (PDT) Reply-To: Mingwei Zhang Date: Mon, 6 May 2024 05:30:01 +0000 In-Reply-To: <20240506053020.3911940-1-mizhang@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240506053020.3911940-1-mizhang@google.com> X-Mailer: git-send-email 2.45.0.rc1.225.g2a3ae87e7f-goog Message-ID: <20240506053020.3911940-37-mizhang@google.com> Subject: [PATCH v2 36/54] KVM: x86/pmu: Switch PMI handler at KVM context switch boundary From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , Mingwei Zhang , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , maobibo , Like Xu , Peter Zijlstra , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org From: Xiong Zhang Switch PMI handler at KVM context switch boundary because KVM uses a separate maskable interrupt vector other than the NMI handler for the host PMU to process its own PMIs. So invoke the perf API that allows registration of the PMI handler. Signed-off-by: Xiong Zhang Signed-off-by: Dapeng Mi --- arch/x86/kvm/pmu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 2ad71020a2c0..a12012a00c11 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -1097,6 +1097,8 @@ void kvm_pmu_save_pmu_context(struct kvm_vcpu *vcpu) if (pmc->counter) wrmsrl(pmc->msr_counter, 0); } + + x86_perf_guest_exit(); } void kvm_pmu_restore_pmu_context(struct kvm_vcpu *vcpu) @@ -1107,6 +1109,8 @@ void kvm_pmu_restore_pmu_context(struct kvm_vcpu *vcpu) lockdep_assert_irqs_disabled(); + x86_perf_guest_enter(kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVTPC)); + static_call_cond(kvm_x86_pmu_restore_pmu_context)(vcpu); /*