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b=B5ieiHlWBDYy8QJDUZEKuBL6yzuY5K7rKN0F33ChRNYS0ZbRo5D9PEY74EBgGbNvvV 0P5w2S2/vlCTHunN8iIRaTEOkUU3vp7HGRamzI0wvqO7OWtEn+Y/DuGhZLtlQ/VMSwEv YJE9UOPlAMSuFU/pDcqwsw5o2Qj7wQdp1xEcbAX3KQ0WFFAv+U+Cg2Kehb3H1NhAswEA q7L/MOu1Tm4Xkusto85eH22Yx904YZDRmvLdObN4PKC2pttasTCKryy2jYx8KLpsQAid EDnJJPPrj3h15d4hWQYq1sPWpm7XgdMQnJPj4LMarWsysNf9kfN3ZiBYstRmeM12ROJb sX8Q== X-Forwarded-Encrypted: i=1; AJvYcCVwA/CGnIuvRtF9qv15/iAIEHKeir+LQMuK2Bqp4Y0k2IzCRwJMHHjEDUao5T3tdamzX7cSkORJgGvBjnXzTGlVlUeT X-Gm-Message-State: AOJu0Yz6Dd9ABXCW22d1jrmT8WysARn9SDlZA9KAi7uO0jmH818tnvRA lnErcaekQ0q9OvK+lHyCzYKnju+UBpNA7I1ldqxTx/nB4xxtygWs5xhmjvHkL4m7atQavi02BLv 5upsaFg== X-Google-Smtp-Source: AGHT+IHYtAKETaSkJtaWjBbjSZv1PW0dYkKkjX2kkHnO+ZOXalrSCVSrUqbKXqRrINppkxEB/rczGUaFb3SL X-Received: from mizhang-super.c.googlers.com ([35.247.89.60]) (user=mizhang job=sendgmr) by 2002:a05:6902:1505:b0:de5:9ecc:46b6 with SMTP id q5-20020a056902150500b00de59ecc46b6mr3476037ybu.6.1714973514144; Sun, 05 May 2024 22:31:54 -0700 (PDT) Reply-To: Mingwei Zhang Date: Mon, 6 May 2024 05:30:11 +0000 In-Reply-To: <20240506053020.3911940-1-mizhang@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240506053020.3911940-1-mizhang@google.com> X-Mailer: git-send-email 2.45.0.rc1.225.g2a3ae87e7f-goog Message-ID: <20240506053020.3911940-47-mizhang@google.com> Subject: [PATCH v2 46/54] perf/x86/amd/core: Set passthrough capability for host From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , Mingwei Zhang , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , maobibo , Like Xu , Peter Zijlstra , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org From: Sandipan Das Apply the PERF_PMU_CAP_PASSTHROUGH_VPMU flag for version 2 and later implementations of the core PMU. Aside from having Global Control and Status registers, virtualizing the PMU using the passthrough model requires an interface to set or clear the overflow bits in the Global Status MSRs while restoring or saving the PMU context of a vCPU. PerfMonV2-capable hardware has additional MSRs for this purpose namely, PerfCntrGlobalStatusSet and PerfCntrGlobalStatusClr, thereby making it suitable for use with passthrough PMU. Signed-off-by: Sandipan Das --- arch/x86/events/amd/core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index 985ef3b47919..7a91c991779c 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -1395,6 +1395,9 @@ static int __init amd_core_pmu_init(void) amd_pmu_global_cntr_mask = (1ULL << x86_pmu.num_counters) - 1; + x86_pmu.flags |= PMU_FL_PASSTHROUGH; + x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_PASSTHROUGH_VPMU; + /* Update PMC handling functions */ x86_pmu.enable_all = amd_pmu_v2_enable_all; x86_pmu.disable_all = amd_pmu_v2_disable_all;