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AJvYcCUBRq8f9HUHN35IHEMcE++w4uYAfIoynptR/U0lSiZWRn3y/Swy+RBWd4lGkgzBEeT4KRX6kaaL6/oZVpzPqZ4FN0YZ X-Gm-Message-State: AOJu0YyMhWiDX5+RIKOdTTFXUmm+AcjaW9aFG5SroM0ChPr3Uxs7Q6vZ 8djc2mR9moGAfJyYI92ayDmK6Y+ZBlMo54MaUCjYsIMpq3m3HyYv4uUSVFiEdxaknmE0m1cgPvj RJgnEyQ== X-Google-Smtp-Source: AGHT+IHCD7D1gafdXvnIaWh5MkPYdDClrelpiWTXntnXJIQreciZAWpYD5dSVRqOOaEkmZpIEOG7CsdVjTmf X-Received: from mizhang-super.c.googlers.com ([34.105.13.176]) (user=mizhang job=sendgmr) by 2002:a17:90b:124e:b0:2b2:b00b:a342 with SMTP id gx14-20020a17090b124e00b002b2b00ba342mr29501pjb.4.1714973526441; Sun, 05 May 2024 22:32:06 -0700 (PDT) Reply-To: Mingwei Zhang Date: Mon, 6 May 2024 05:30:18 +0000 In-Reply-To: <20240506053020.3911940-1-mizhang@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240506053020.3911940-1-mizhang@google.com> X-Mailer: git-send-email 2.45.0.rc1.225.g2a3ae87e7f-goog Message-ID: <20240506053020.3911940-54-mizhang@google.com> Subject: [PATCH v2 53/54] KVM: x86/pmu/svm: Implement handlers to save and restore context From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , Mingwei Zhang , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , maobibo , Like Xu , Peter Zijlstra , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org From: Sandipan Das Implement the AMD-specific handlers to save and restore the state of PMU-related MSRs when using passthrough PMU. Signed-off-by: Sandipan Das --- arch/x86/kvm/svm/pmu.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index bed0acfaf34d..9629a172aa1b 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -295,6 +295,36 @@ static void amd_passthrough_pmu_msrs(struct kvm_vcpu *vcpu) set_msr_interception(vcpu, svm->msrpm, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET, msr_clear, msr_clear); } +static void amd_save_pmu_context(struct kvm_vcpu *vcpu) +{ + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + + rdmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, pmu->global_ctrl); + wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0); + rdmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, pmu->global_status); + + /* Clear global status bits if non-zero */ + if (pmu->global_status) + wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, pmu->global_status); +} + +static void amd_restore_pmu_context(struct kvm_vcpu *vcpu) +{ + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + u64 global_status; + + wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0); + rdmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, global_status); + + /* Clear host global_status MSR if non-zero. */ + if (global_status) + wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, global_status); + + wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET, pmu->global_status); + + wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, pmu->global_ctrl); +} + struct kvm_pmu_ops amd_pmu_ops __initdata = { .rdpmc_ecx_to_pmc = amd_rdpmc_ecx_to_pmc, .msr_idx_to_pmc = amd_msr_idx_to_pmc, @@ -306,6 +336,8 @@ struct kvm_pmu_ops amd_pmu_ops __initdata = { .init = amd_pmu_init, .is_rdpmc_passthru_allowed = amd_is_rdpmc_passthru_allowed, .passthrough_pmu_msrs = amd_passthrough_pmu_msrs, + .save_pmu_context = amd_save_pmu_context, + .restore_pmu_context = amd_restore_pmu_context, .EVENTSEL_EVENT = AMD64_EVENTSEL_EVENT, .MAX_NR_GP_COUNTERS = KVM_AMD_PMC_MAX_GENERIC, .MIN_NR_GP_COUNTERS = AMD64_NUM_COUNTERS,