From patchwork Mon May 6 08:51:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13655122 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BED01422C4 for ; Mon, 6 May 2024 08:37:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714984679; cv=none; b=aPl8aZ8SVkSW4SzhnL2qAf22BOMUNZz7VmyV3qXAZ7q4sa+jfHw398JZKh6y6b+cuAVC8BvCOJR+1sH1eSfyGAMPebNV27z5Ugd439/7sneAJMDsETfuw6QTPDZ6j9zUqMPk4wDWSI/JoR9wccE/dyrJ9173rdc0GUY0xpfdx84= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714984679; c=relaxed/simple; bh=DB2VwZXinBeu85sxU2DvMAYIhQta93ZmsODncoEIuQc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WK3e1yj+UDppNVskPYVJPFNCq4oJTMkcWSkLL/A4HHXM+AySuviTFwEUQFGjokuK+nXoYdchlVnDkUzj4CGcRuKKFc1zcrolqOJknLj3oGnlX+eKqSEyMvRJvZkgH+fA7E1vlLWNNLfAsHCD9V/fCX3GGYZrqiB6+6xy+bFpyLk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mndaRBL4; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mndaRBL4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714984678; x=1746520678; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DB2VwZXinBeu85sxU2DvMAYIhQta93ZmsODncoEIuQc=; b=mndaRBL4TjPCtpse4drROqAs++/OlV3i+oFv4cHuDJ5y3o4fbq1gQuVv 21wsvj+kcj06Io+PG/P9Wn0AUoPZX5huMlVKTusAJ6v8UvpDUXgcqJ+Aa SpoxHv4u1UlP2ybMZfUfPx8uXJRnskjXaQwwyqTHn42F298QsrP3dDWal pNJJkUr1wL4uQGW6IPbU2md2k5HabCH6luDDHrz/P+vdGNA4izdaU8YLA 2Ie/Ax7TB/zS5WIRl6ZDSOCisc1tfykKJdWg/2qj5bSjbJQW+NEBc3W0d T7OPxlCCFgY63NCZZW4jLeAk66g5pyMqj27XWXIDZCx5thjqfkJXlA0DE g==; X-CSE-ConnectionGUID: eycgPqPUS6yDCwODye3LPw== X-CSE-MsgGUID: ydKnfHasRomAOIleaAAT3A== X-IronPort-AV: E=McAfee;i="6600,9927,11064"; a="14533356" X-IronPort-AV: E=Sophos;i="6.07,257,1708416000"; d="scan'208";a="14533356" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2024 01:37:58 -0700 X-CSE-ConnectionGUID: Qxo1myYsRWyyg3bZiQU5JQ== X-CSE-MsgGUID: beAxgUupSKusCfH+tGL85g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,257,1708416000"; d="scan'208";a="28186742" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa010.fm.intel.com with ESMTP; 06 May 2024 01:37:55 -0700 From: Zhao Liu To: Paolo Bonzini , Richard Henderson , Eduardo Habkost , "Michael S . Tsirkin" , Marcel Apfelbaum , Marcelo Tosatti Cc: Xiaoyao Li , Pankaj Gupta , Zide Chen , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH v2 4/6] target/i386/kvm: Save/load MSRs of kvmclock2 (KVM_FEATURE_CLOCKSOURCE2) Date: Mon, 6 May 2024 16:51:51 +0800 Message-Id: <20240506085153.2834841-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240506085153.2834841-1-zhao1.liu@intel.com> References: <20240506085153.2834841-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 MSR_KVM_SYSTEM_TIME_NEW and MSR_KVM_WALL_CLOCK_NEW are bound to kvmclock2 (KVM_FEATURE_CLOCKSOURCE2). Add the save/load support for these 2 MSRs just like kvmclock MSRs. Signed-off-by: Zhao Liu --- target/i386/cpu.h | 2 ++ target/i386/kvm/kvm.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 66948c68616e..e61db78550fe 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1738,6 +1738,8 @@ typedef struct CPUArchState { uint64_t system_time_msr; uint64_t wall_clock_msr; + uint64_t system_time_new_msr; + uint64_t wall_clock_new_msr; uint64_t steal_time_msr; uint64_t async_pf_en_msr; uint64_t async_pf_int_msr; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 75d2091c4f8c..ee0767e8f501 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -3376,6 +3376,12 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr); kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr); } + if (env->features[FEAT_KVM] & CPUID_KVM_CLOCK2) { + kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME_NEW, + env->system_time_new_msr); + kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK_NEW, + env->wall_clock_new_msr); + } if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF_INT) { kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr); } @@ -3843,6 +3849,10 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0); kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0); } + if (env->features[FEAT_KVM] & CPUID_KVM_CLOCK2) { + kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME_NEW, 0); + kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK_NEW, 0); + } if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF_INT) { kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0); } @@ -4082,6 +4092,12 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_KVM_WALL_CLOCK: env->wall_clock_msr = msrs[i].data; break; + case MSR_KVM_SYSTEM_TIME_NEW: + env->system_time_new_msr = msrs[i].data; + break; + case MSR_KVM_WALL_CLOCK_NEW: + env->wall_clock_new_msr = msrs[i].data; + break; case MSR_MCG_STATUS: env->mcg_status = msrs[i].data; break;