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([2a01:e0a:999:a3a0:46f0:3724:aa77:c1f8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4200e518984sm240669275e9.23.2024.05.17.06.40.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 06:40:11 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Andrew Jones , Anup Patel , Atish Patra Subject: [kvm-unit-tests PATCH v1 1/4] riscv: move REG_L/REG_W in a dedicated asm.h file Date: Fri, 17 May 2024 15:40:02 +0200 Message-ID: <20240517134007.928539-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240517134007.928539-1-cleger@rivosinc.com> References: <20240517134007.928539-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 These assembly macros will be used as part of the SSE entry assembly code, export them in asm.h header. Signed-off-by: Clément Léger --- lib/riscv/asm/asm.h | 19 +++++++++++++++++++ riscv/cstart.S | 14 +------------- 2 files changed, 20 insertions(+), 13 deletions(-) create mode 100644 lib/riscv/asm/asm.h diff --git a/lib/riscv/asm/asm.h b/lib/riscv/asm/asm.h new file mode 100644 index 00000000..763b28e6 --- /dev/null +++ b/lib/riscv/asm/asm.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASMRISCV_ASM_H_ +#define _ASMRISCV_ASM_H_ + +#if __riscv_xlen == 64 +#define __REG_SEL(a, b) a +#elif __riscv_xlen == 32 +#define __REG_SEL(a, b) b +#else +#error "Unexpected __riscv_xlen" +#endif + +#define REG_L __REG_SEL(ld, lw) +#define REG_S __REG_SEL(sd, sw) +#define SZREG __REG_SEL(8, 4) + +#define FP_SIZE 16 + +#endif /* _ASMRISCV_ASM_H_ */ diff --git a/riscv/cstart.S b/riscv/cstart.S index 10b5da57..d5d8ad25 100644 --- a/riscv/cstart.S +++ b/riscv/cstart.S @@ -4,22 +4,10 @@ * * Copyright (C) 2023, Ventana Micro Systems Inc., Andrew Jones */ +#include #include #include -#if __riscv_xlen == 64 -#define __REG_SEL(a, b) a -#elif __riscv_xlen == 32 -#define __REG_SEL(a, b) b -#else -#error "Unexpected __riscv_xlen" -#endif - -#define REG_L __REG_SEL(ld, lw) -#define REG_S __REG_SEL(sd, sw) -#define SZREG __REG_SEL(8, 4) - -#define FP_SIZE 16 .macro push_fp, ra=ra addi sp, sp, -FP_SIZE