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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS2PEPF00003443.mail.protection.outlook.com (10.167.17.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7633.15 via Frontend Transport; Fri, 31 May 2024 04:47:16 +0000 Received: from BLR-L-RBANGORI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 30 May 2024 23:47:11 -0500 From: Ravi Bangoria To: , , CC: , , , , , , , , , , , , Subject: [PATCH v4 2/3] KVM: SEV-ES: Disallow SEV-ES guests when X86_FEATURE_LBRV is absent Date: Fri, 31 May 2024 04:46:43 +0000 Message-ID: <20240531044644.768-3-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240531044644.768-1-ravi.bangoria@amd.com> References: <20240531044644.768-1-ravi.bangoria@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003443:EE_|PH7PR12MB5595:EE_ X-MS-Office365-Filtering-Correlation-Id: b360a9b4-f8d5-4921-c767-08dc812cbf5e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|1800799015|376005|7416005|36860700004; X-Microsoft-Antispam-Message-Info: 6uK3gG08kNr+z24Z2QNksL6ilDlvRtJ+YsCl6usf86WYa+N3gzDYWgxLmStC9K7HY2x9C6rAgpqGsB0epa7dzZpSqSZAYhaj3tnO/rgJKxzhviSLvtgpHPJx6bhPn8MzHsnHmcKFbxOKKkLLv7AFAwYH/GSGdF03zPiSYrhKkaRX5Bkww13GAL99Dk2we12snjDsjGJcpIxXIpbW2qIotVG405mxN8caGz014wMmra8wfOffn+4Kn8JJGB/P7EkwzjlKtqdxICkU0WXR8aT6z+Zy0ymMHDhGHg4Gdq9h9R5+gXx3olC9OqIfG7IClflgyTliWxVAe+280JxexHJ75af4X3oUPcnABy+/L2Rhp4IpxdqJrbrAOdxryPxQF4LLNJ/XWAu4yOv/dwjWfk5WGhopWoJZOw9o+6TtO8SEm0MOOtb6HiohqlOznpHscoJ1qPzeCTh0P39UxcPBFYPS0Hhp24YfrBWRhx0wm+b4o1uMiZEyCskncPDT3CbDGfGXHVy1pgLK4QuDPSKKeigHxZXEOYm/kjU3cZC0FMswyp8aYiyyI6TldpAY5mL7lufWuog4r1eUDCJcTYShE1NC6yv616voGPIREzWAzS49814oOEaOTg7vi9n+ng93aFcRRY+qt+ljMg7SQCrk5dEFsk4l6qS6pSI1I674660y0NonvRxw+wLVvQpCquia8jXw3cqQW1m/7yzHRfFztBm2IoLLBsQJU2dahrhRBu8xGqZnTNHjrK1OppIbVnvEvCYscu7ErZCA5pE82KURviuzbLr1M3hbhjAMQnM/wQ9OjQxI1D7JD7JZx5XckCO92E6R29AS1pQRSBmE2tug2dTyiJ3wUm8WHNQmMlxjp4/RIatQZ85FRlO//MetAxlJjBmXI74ZnCWodaKuFWktVFN20TFAcTehH6P0yabzSxSA+nQ7WJuz32f/f0z1qeyfoVX4W21fXNP+dJUaZoGPCu51LB/isA45ffS9nGODE7wlmPls8G22QoeotyB08q5UvO68Z9phuieVqYQhTqIetm/R72WUJKWgi29bsljs5hoj81zSb6X7bFMui5lICd5Xo/hhclA3Gc8HH0dm0UR5+AvCHFYIvlY3eL0ogDHX7w6Vx7BQvpGTWGygKUfbskLizJtjnm0Tg1Y5RlHVb6MNdXwQFwE6jyRoqnHAOtT13C6KstoO/gk9o7wR0DN/hFKk41aheTjMHKc4zsoKjMLuaYAzA9sQR/kcqMnLJM0ze2OhwTgrDBiCsyBu7H51JAY2noDMYlmXNpniWH0H1JPLP5W3FwMuBlrjTL4q8wOzwB+Snbs81oUg1G0yvL+RLXHwSh8X X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(82310400017)(1800799015)(376005)(7416005)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 May 2024 04:47:16.8034 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b360a9b4-f8d5-4921-c767-08dc812cbf5e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003443.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5595 As documented in APM[1], LBR Virtualization must be enabled for SEV-ES guests. So, prevent SEV-ES guests when LBRV support is missing. [1]: AMD64 Architecture Programmer's Manual Pub. 40332, Rev. 4.07 - June 2023, Vol 2, 15.35.2 Enabling SEV-ES. https://bugzilla.kernel.org/attachment.cgi?id=304653 Fixes: 376c6d285017 ("KVM: SVM: Provide support for SEV-ES vCPU creation/loading") Signed-off-by: Ravi Bangoria --- arch/x86/kvm/svm/sev.c | 6 ++++++ arch/x86/kvm/svm/svm.c | 16 +++++++--------- arch/x86/kvm/svm/svm.h | 1 + 3 files changed, 14 insertions(+), 9 deletions(-) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 176ba117413a..8345a5098ab7 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -2933,6 +2933,12 @@ void __init sev_hardware_setup(void) if (!boot_cpu_has(X86_FEATURE_SEV_ES)) goto out; + if (!lbrv) { + WARN_ONCE(!boot_cpu_has(X86_FEATURE_LBRV), + "LBRV must be present for SEV-ES support"); + goto out; + } + /* Has the system been allocated ASIDs for SEV-ES? */ if (min_sev_asid == 1) goto out; diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 1a01293f6909..cadf3085f183 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -215,7 +215,7 @@ int vgif = true; module_param(vgif, int, 0444); /* enable/disable LBR virtualization */ -static int lbrv = true; +int lbrv = true; module_param(lbrv, int, 0444); static int tsc_scaling = true; @@ -5308,6 +5308,12 @@ static __init int svm_hardware_setup(void) nrips = nrips && boot_cpu_has(X86_FEATURE_NRIPS); + if (lbrv) { + if (!boot_cpu_has(X86_FEATURE_LBRV)) + lbrv = false; + else + pr_info("LBR virtualization supported\n"); + } /* * Note, SEV setup consumes npt_enabled and enable_mmio_caching (which * may be modified by svm_adjust_mmio_mask()), as well as nrips. @@ -5361,14 +5367,6 @@ static __init int svm_hardware_setup(void) svm_x86_ops.set_vnmi_pending = NULL; } - - if (lbrv) { - if (!boot_cpu_has(X86_FEATURE_LBRV)) - lbrv = false; - else - pr_info("LBR virtualization supported\n"); - } - if (!enable_pmu) pr_info("PMU virtualization is disabled\n"); diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 555c55f50298..2d6c19c55b1a 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -39,6 +39,7 @@ extern int vgif; extern bool intercept_smi; extern bool x2avic_enabled; extern bool vnmi; +extern int lbrv; /* * Clean bits in VMCB.