From patchwork Fri May 31 09:03:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yang, Weijiang" X-Patchwork-Id: 13681346 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD5AA15689B; Fri, 31 May 2024 09:04:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717146244; cv=none; b=BosxhM7c3VeteZYaM2g6aMn1OEnpV68MnGVFJpjq7pSeSvIV+OQ+kmMRraidwuJsldtp3G2ZjxmpgxwItJwvu+nT9IF6sBeYPIp1WupdrcEYLIRjEnNk0skvdnE1pYTJrTyILAEsdi+Srb7AVs9b9Mre9f5WdBl00FkmgE38wfo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717146244; c=relaxed/simple; bh=XHJjqKGhN585X7aLvVu2CbdGCurM4gt6+uoq5Ic29mQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=I4NQQg+4XzXwD8y85KxsRkLFU7/HXOiSf5Goffg3EDgClIjbzym5ZWky87YB8wfMXws2jGv5rXLnteVNZNV3ECwzkgGBEslpOxT4JGfrN3pk/67ouBoF63GKLX8Jr5fKJYKD5lojhBA2xXL2cV3/KNEGHkzDizC+2SqivHwJHh0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EL7e6Pya; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EL7e6Pya" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717146243; x=1748682243; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XHJjqKGhN585X7aLvVu2CbdGCurM4gt6+uoq5Ic29mQ=; b=EL7e6PyayPUmhQ0x1F9zgxKiCFWxCfRA7OvVTI+FtO7fZEvxVv7zpoga TCK46WYVuOrteoZD3YJXOzAN5IzLqZGWJoQRxBKr/PYWWuPqrIQ+ugtQ1 dL7VcKXSNm3/bh8oE7LkrGzNX1AfqRA8c4IxP+55l4gh+TBDyxIIUzQpg RN5Og18ATgwnuhV0Lb57rLHx9nF/Pm/ASGKRCXecYSNVYQp55wkFmwrph bXYyvJLT590tv4a3SCssQyF3WcFgVKmeLp0q1mI4FQ7ca+V7jcILxOBxZ ArA2zq+hhIMubCWPp0hpXig2USswRFv1A712NsLk0iSKLkXZCtLT2mtXz g==; X-CSE-ConnectionGUID: KD1FglHsTEOdTYBfD/ROPQ== X-CSE-MsgGUID: KX72JwJ9QVmo0GUF5NbTFQ== X-IronPort-AV: E=McAfee;i="6600,9927,11088"; a="17480614" X-IronPort-AV: E=Sophos;i="6.08,203,1712646000"; d="scan'208";a="17480614" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2024 02:04:00 -0700 X-CSE-ConnectionGUID: pHRfIuaaTOisDoUHZY+0XA== X-CSE-MsgGUID: kUyLSYosQE+CVKNchuXdgw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,203,1712646000"; d="scan'208";a="36102754" Received: from jf.jf.intel.com ([10.165.9.183]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2024 02:04:00 -0700 From: Yang Weijiang To: tglx@linutronix.de, dave.hansen@intel.com, x86@kernel.org, seanjc@google.com, pbonzini@redhat.com, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: peterz@infradead.org, chao.gao@intel.com, rick.p.edgecombe@intel.com, mlevitsk@redhat.com, weijiang.yang@intel.com, john.allen@amd.com Subject: [PATCH 5/6] x86/fpu/xstate: Create guest fpstate with guest specific config Date: Fri, 31 May 2024 02:03:30 -0700 Message-ID: <20240531090331.13713-6-weijiang.yang@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240531090331.13713-1-weijiang.yang@intel.com> References: <20240531090331.13713-1-weijiang.yang@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use fpu_guest_cfg to calculate guest fpstate settings, open code for __fpstate_reset() to avoid using kernel FPU config. Below configuration steps are currently enforced to get guest fpstate: 1) Kernel sets up guest FPU settings in fpu__init_system_xstate(). 2) User space sets vCPU thread group xstate permits via arch_prctl(). 3) User space creates guest fpstate via __fpu_alloc_init_guest_fpstate() for vcpu thread. 4) User space enables guest dynamic xfeatures and re-allocate guest fpstate. By adding kernel dynamic xfeatures in above #1 and #2, guest xstate area size is expanded to hold (fpu_kernel_cfg.default_features | kernel dynamic xfeatures | user dynamic xfeatures), then host xsaves/xrstors can operate for all guest xfeatures. The user_* fields remain unchanged for compatibility with KVM uAPIs. Signed-off-by: Yang Weijiang Reviewed-by: Maxim Levitsky Reviewed-by: Rick Edgecombe --- arch/x86/kernel/fpu/core.c | 39 +++++++++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index 9e2e5c46cf28..00d7dcf45b34 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -194,8 +194,6 @@ void fpu_reset_from_exception_fixup(void) } #if IS_ENABLED(CONFIG_KVM) -static void __fpstate_reset(struct fpstate *fpstate, u64 xfd); - static void fpu_init_guest_permissions(struct fpu_guest *gfpu) { struct fpu_state_perm *fpuperm; @@ -216,25 +214,48 @@ static void fpu_init_guest_permissions(struct fpu_guest *gfpu) gfpu->perm = perm & ~FPU_GUEST_PERM_LOCKED; } -bool fpu_alloc_guest_fpstate(struct fpu_guest *gfpu) +static struct fpstate *__fpu_alloc_init_guest_fpstate(struct fpu_guest *gfpu) { struct fpstate *fpstate; unsigned int size; - size = fpu_user_cfg.default_size + ALIGN(offsetof(struct fpstate, regs), 64); + /* + * fpu_guest_cfg.default_size is initialized to hold all enabled + * xfeatures except the user dynamic xfeatures. If the user dynamic + * xfeatures are enabled, the guest fpstate will be re-allocated to + * hold all guest enabled xfeatures, so omit user dynamic xfeatures + * here. + */ + size = fpu_guest_cfg.default_size + ALIGN(offsetof(struct fpstate, regs), 64); + fpstate = vzalloc(size); if (!fpstate) - return false; + return NULL; + /* + * Initialize sizes and feature masks, use fpu_user_cfg.* + * for user_* settings for compatibility of exiting uAPIs. + */ + fpstate->size = fpu_guest_cfg.default_size; + fpstate->xfeatures = fpu_guest_cfg.default_features; + fpstate->user_size = fpu_user_cfg.default_size; + fpstate->user_xfeatures = fpu_user_cfg.default_features; + fpstate->xfd = 0; - /* Leave xfd to 0 (the reset value defined by spec) */ - __fpstate_reset(fpstate, 0); fpstate_init_user(fpstate); fpstate->is_valloc = true; fpstate->is_guest = true; gfpu->fpstate = fpstate; - gfpu->xfeatures = fpu_user_cfg.default_features; - gfpu->perm = fpu_user_cfg.default_features; + gfpu->xfeatures = fpu_guest_cfg.default_features; + gfpu->perm = fpu_guest_cfg.default_features; + + return fpstate; +} + +bool fpu_alloc_guest_fpstate(struct fpu_guest *gfpu) +{ + if (!__fpu_alloc_init_guest_fpstate(gfpu)) + return false; /* * KVM sets the FP+SSE bits in the XSAVE header when copying FPU state