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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF0000C37D.mail.protection.outlook.com (10.167.23.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Fri, 21 Jun 2024 12:40:34 +0000 Received: from gomati.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 21 Jun 2024 07:40:30 -0500 From: Nikunj A Dadhania To: , , , , CC: , , , , , , Subject: [PATCH v10 19/24] x86/sev: Change TSC MSR behavior for Secure TSC enabled guests Date: Fri, 21 Jun 2024 18:08:58 +0530 Message-ID: <20240621123903.2411843-20-nikunj@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240621123903.2411843-1-nikunj@amd.com> References: <20240621123903.2411843-1-nikunj@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37D:EE_|CY8PR12MB8363:EE_ X-MS-Office365-Filtering-Correlation-Id: 484ede7a-b5a2-4db3-0157-08dc91ef58a7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|82310400023|36860700010|376011|7416011|1800799021; X-Microsoft-Antispam-Message-Info: olapYLXME1sm5hb3srjcsFmESS++BhPCT9EYIhHcS0IRw3NB7ZmIiwn+IqL7uN6LXRBIflBG2cDleEroO7lsgcmXhoKhbjBzPL7cOzfJdVPQOF9lRYl7zWl+QdLw93oxsMD1OhVyfAYhA5YblXKIssIYyPb4aEWaV/wiWTnSlXbsvy+uxzkTVjtMTKKFUbs5JxHtxMsgKDjdOKu8AnImM+ixSagSFluvFzx5neS2lg+Zecsnop18jwdlwdqGrVYJOQ80uXfAH2C1qP7/57pkLBfgiOc+xIm41ayEf1PKh/hLiZhsHx7kR1ucOJOWpaCjDFqbmZyyA6aKCi7lv1iAnRR/CHVrlpjkDURe4I0VtzzD4K/KHnvlvcqFrnEq93MGQwsnqO7MUbx7ussEe6/00mTpRTcPE9rQEXFwRUj8Q2sJqSE0lzc1M+nX4aaQirpKAsX355oZ5gQj93q0O1idzo8vwPgDOghkulV1WIUTBzo+0aIAUUw0WfzJG/dYgk1T4XQEdyen++efVBAN1D6Ga6wnR4MtKRAUUGdeYLXPvH0fIFmUcGErrdKjytCRUlowOaDqI4c9qEL3Eot8Q/4yz3ImNWwDrMKH5ojWLu4UwOZ7ilx/mRgTYSipcY6/p45M+N2leCcDwlLOsE0PYAWGp/VIoOHh+8R5MM5NvBxUbjlx7iokgSMzQmrBTOBo8USkqygFdA5HfWKsYp9ZuVU7RXLbvI+64pWZbhXIdSq4cfXDQrqAY2rc41EcuHo6E5u4Fgimg3rOkQSag6zqa1bVV8i8oo3i6nq54WYdi2pw7wDVdS8n9VEb87Uj0gAtKDv3qHIxnQTA2jA7bVo9I21Nq6Wd1rPpysZHDE9KCVWOXhFalX9oFwB8HwcKfa+/EOYgd2HpmioTilvzm39z7YSp5j/PL+gdnl1PTLBqA2Yc3tYkmhAIMGZWQajBORPdr4r5BRDQgKFmco0GvlJAWktRSObtYHNKrwh12wyCNsZpMjgoM+iR4NpPlJx6reCaLBjFo8Pnhk9+5F7Hm5BUD7ZDopiERQRbXpdLIOWqWNyvntKw0lWRoGuukqNFq5t+pfZtDmc4s7RXkvRdEkv4vdT0KhzPRKhVpIjPBoZZQV6oLYjV6qxvH6+DSReKSp4394uuE3kZX2Vnbnsag5t/7jWlrP3a2WJyId634yy620aOv/SUmZSYXjQMjBmIl/B+Wk8pTBnphSuo0t5Qbs/XUueHMDli2tt7pikO4GFEJ7wBsauEJtqp4VPOCt3DqXCNWmyb1o/S08Cng7lGT0H0sA+TMpqNCNtlsaBBWlZOO2Xpn54OdswAovQhdYSS6+LfQ6QJE0U5wHAKnmNLDC7D/gBzHH5LkYVHwootBRu6PLH9Q+pMcF2Wde8G08TK5Q93bbmIsQnJMHs6tYJUU1NBLJ5sbw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(82310400023)(36860700010)(376011)(7416011)(1800799021);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2024 12:40:34.9381 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 484ede7a-b5a2-4db3-0157-08dc91ef58a7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8363 Secure TSC enabled guests should not write MSR_IA32_TSC(10H) register as the subsequent TSC value reads are undefined. MSR_IA32_TSC related accesses should not exit to the hypervisor for such guests. Accesses to MSR_IA32_TSC needs special handling in the #VC handler for the guests with Secure TSC enabled. Writes to MSR_IA32_TSC should be ignored, and reads of MSR_IA32_TSC should return the result of the RDTSC instruction. Signed-off-by: Nikunj A Dadhania Reviewed-by: Tom Lendacky Tested-by: Peter Gonda --- arch/x86/coco/sev/core.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c index 7aed6819930b..fda40794317e 100644 --- a/arch/x86/coco/sev/core.c +++ b/arch/x86/coco/sev/core.c @@ -1333,6 +1333,30 @@ static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt) return ES_OK; } + /* + * TSC related accesses should not exit to the hypervisor when a + * guest is executing with SecureTSC enabled, so special handling + * is required for accesses of MSR_IA32_TSC: + * + * Writes: Writing to MSR_IA32_TSC can cause subsequent reads + * of the TSC to return undefined values, so ignore all + * writes. + * Reads: Reads of MSR_IA32_TSC should return the current TSC + * value, use the value returned by RDTSC. + */ + if (regs->cx == MSR_IA32_TSC && cc_platform_has(CC_ATTR_GUEST_SECURE_TSC)) { + u64 tsc; + + if (exit_info_1) + return ES_OK; + + tsc = rdtsc(); + regs->ax = UINT_MAX & tsc; + regs->dx = UINT_MAX & (tsc >> 32); + + return ES_OK; + } + ghcb_set_rcx(ghcb, regs->cx); if (exit_info_1) { ghcb_set_rax(ghcb, regs->ax);