From patchwork Thu Jul 4 03:16:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13723138 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91ACC1BC23 for ; Thu, 4 Jul 2024 03:01:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720062065; cv=none; b=eT6SEB+WXaojucDR/iK224jOaZY1eVhoF398bqFaDRDZZGV9bPyrgZAcziTfnRM0ZrYL6X496wuywax9NHJludATUalTPAGQ+7hoiE507I+wpAzGsaDoBMgsHOg9OceDfqDyZ8IrIWGZovP4Ihj8YtV8VTGrqHyoYpSlfUHBRUU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720062065; c=relaxed/simple; bh=fujCsC8Dys68Pql9dJtKAju+zQdGhBxq4c+kPZSh5nE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=S4fbcpWYSmjyJSoK4nUZQDZWe3+8VfrbXaLKrenfAPBOJEbmOXVD9n5DPnn44hq41p1jqUKAudLf0ZqzG25ipevOxxpipRD4GPU/xTESpfRRtTodhZl//y7tTQ3EcA/Ek5HeYTkr2JJCuB82d3OGhJ7EvUvrrI8k8mPAfazgfqE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DBgWmsH9; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DBgWmsH9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1720062064; x=1751598064; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fujCsC8Dys68Pql9dJtKAju+zQdGhBxq4c+kPZSh5nE=; b=DBgWmsH9IrGbrPuSTzHt3Txpl4PfHO4gUo2Q5gNp5nMkm+Wbt0n/N8G3 T+KJkXNZMusFNC9ag1D1SWAlgiQO6a5SQ/Z9cbAGxnqgulNdL1HBXX2ZI zRegFH8MY8GPgHdTWzdo4h7trlPTounIeCTi+cueSJkITsUj+nMKJUv4T r0h/UgpB3SyiI+xKx+ta8T2f4o8kqjO8WoYPDe57tioOUUTTPqDQ5QnCB OQs/cK5n6wq5b/Fd+YhYRWuykDnEwVhpt8aOP8Rv0tNZFvRQe0NkpDXMf /ML9HJyzyv0GMZlYpdLOrxmNEQAdXruDtYUklG2U0Aa6NHM4S2gMjLj2t g==; X-CSE-ConnectionGUID: odQ+FStZQCOWTdTI4qE+lg== X-CSE-MsgGUID: 4FHRB40qSUiWPPAPvqDG8w== X-IronPort-AV: E=McAfee;i="6700,10204,11122"; a="39838138" X-IronPort-AV: E=Sophos;i="6.09,183,1716274800"; d="scan'208";a="39838138" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2024 20:01:03 -0700 X-CSE-ConnectionGUID: SWw29a7FTiSSxRr5IbNo7w== X-CSE-MsgGUID: P2ER7FN4T+qcoemaxtpO5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,183,1716274800"; d="scan'208";a="51052438" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa004.fm.intel.com with ESMTP; 03 Jul 2024 20:00:58 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH 6/8] i386/cpu: Update cache topology with machine's configuration Date: Thu, 4 Jul 2024 11:16:01 +0800 Message-Id: <20240704031603.1744546-7-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240704031603.1744546-1-zhao1.liu@intel.com> References: <20240704031603.1744546-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User will configure smp cache topology via smp-cache object. For this case, update the x86 CPUs' cache topology with user's configuration in MachineState. Signed-off-by: Zhao Liu --- Changes since RFC v2: * Used smp_cache array to override cache topology. * Wrapped the updating into a function. --- target/i386/cpu.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0ddbfa577caf..403a089111ca 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7568,6 +7568,38 @@ static void x86_cpu_hyperv_realize(X86CPU *cpu) cpu->hyperv_limits[2] = 0; } +#ifndef CONFIG_USER_ONLY +static void x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu) +{ + CPUX86State *env = &cpu->env; + CpuTopologyLevel level; + + level = machine_get_cache_topo_level(ms, SMP_CACHE_L1D); + if (level != CPU_TOPO_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l1d_cache->share_level = level; + env->cache_info_amd.l1d_cache->share_level = level; + } + + level = machine_get_cache_topo_level(ms, SMP_CACHE_L1I); + if (level != CPU_TOPO_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l1i_cache->share_level = level; + env->cache_info_amd.l1i_cache->share_level = level; + } + + level = machine_get_cache_topo_level(ms, SMP_CACHE_L2); + if (level != CPU_TOPO_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l2_cache->share_level = level; + env->cache_info_amd.l2_cache->share_level = level; + } + + level = machine_get_cache_topo_level(ms, SMP_CACHE_L3); + if (level != CPU_TOPO_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l3_cache->share_level = level; + env->cache_info_amd.l3_cache->share_level = level; + } +} +#endif + static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -7792,6 +7824,11 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) #ifndef CONFIG_USER_ONLY MachineState *ms = MACHINE(qdev_get_machine()); + + if (ms->smp_cache) { + x86_cpu_update_smp_cache_topo(ms, cpu); + } + qemu_register_reset(x86_cpu_machine_reset_cb, cpu); if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {