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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF0000C37D.mail.protection.outlook.com (10.167.23.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7828.19 via Frontend Transport; Wed, 31 Jul 2024 15:09:45 +0000 Received: from gomati.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 31 Jul 2024 10:09:41 -0500 From: Nikunj A Dadhania To: , , , , CC: , , , , , , Subject: [PATCH v11 20/20] x86/cpu/amd: Do not print FW_BUG for Secure TSC Date: Wed, 31 Jul 2024 20:38:11 +0530 Message-ID: <20240731150811.156771-21-nikunj@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240731150811.156771-1-nikunj@amd.com> References: <20240731150811.156771-1-nikunj@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37D:EE_|DM6PR12MB4137:EE_ X-MS-Office365-Filtering-Correlation-Id: 2431b0ee-0c4d-4678-e36d-08dcb172d009 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|7416014|1800799024; X-Microsoft-Antispam-Message-Info: elEgJjT5FbuQ8tfjLqoqI5eFNWzyijAjWL+kZt1sHfuTX3QLTH+oLGgCdLFHFNrkdESnAg+tdwDofX+E8XNxL6HwCwtGLHQJZwePn8gVapzkSXYBBlUjjtOLmhbltsIdVwOwWHmW/QRErlDUOS7xT91u/vdtaYi6blheDkKnadRuqa6cjx1l0B2fgK1kFKvEieWMq/9ASVOgpaMTysYR04ELXu7liS/dKBOhFTE5+nF+iNnAo6FZ134TZAIaM+f4BfugeWrvOTJDYvqo+qD6LAng8MCVWzhpO8pbXj9KVl0vaRcoXQ72H8OCf8F8HMUO1fuImlO0odzRqSmKBo5cxh8KxNnFKqGWOu5+j2thMRuuPzPlVLwxjrEAbG23hW6ns0iq7bg05uEFZ142J9f3HRXXrY+QiqN+IVJbfnoNf1LZI96K0jbuKxpie+KVrgybOcouFUFwzs1/uRF1hq9HvSlQfXI9uUNA9izLhSYlrGmpkCNBYCE9Mhpt5lURk7rh8KLIEUNZ0JwEbP7aVdrl8Vvxkg2gm+juT9J4u0E+9t66o9yOJtewqH3yaxZKlOHd47+ga2ASClrzTNWCJKl4vOSB6XMLP5+e2eZ0XJzBhi7suMmm9JU4qz4MsBInLJK+d9y5KfT3mSjU4Rhvrbhjy8LgzYiLEje4++/D0uytdc2Zp7uUFS3fq/A09z5g3GdMc++MOgeLUecrb7QOBGEH1Ipp9oDB+OIzJYxekOiA/EStf80gTcpk+/cqNGVpoUXeC8S37YFrFu+HuolHMPPCBF0nnXqJcfyHtQv1Q9ufhuxS4p9dhClBg6kdvUXw4x3SnqtBU+oDNmR3Pqm61Yt6JU9h2orvRxPyBAV/gvYRTcsLvvQhRvnmk14vyldrG4tH8N6qSPGXpZ707snv7rnrEqTIvHy7BiwjgowJZ+qV5dNHoUXaBftBat1sxOZ5tGx5wMxMts9ygjFy/Z0JAc4nOoUnt0kIT3iyx7AdUzjCAiEnRLE5PbHJxiVcGNWnj8zxKRkO1V6JSrF4KQHNXrdPSDaSHpB8qCsYj9JcirBfGN4GVZGA//J0BHEErxvQVs8qKrwVOKh633U0Co8ty4THRRaTIvgNJ+XHt+gpBm5FHS6TXcgC4SgGAlpqRmqcAhQyeOLMonwqPbblzZWFYFWYRZegzPTu2etZdXoo2SL75rS14gLFw96G/QKLT5FbjQlYr2NMi4MsgVSB5UlUYRSfzkEDPgV3xTAc3lzgOncgvaVLrKHeRBjlEdCC1cndahD59Y3ux+TJLLFZogdGv3VNBsBnZwAhNKLcOdhiV6LGN53U5h0Ryp/qJZ9xML7FQ63Wc58Bf1+243Ce/CTn/xWaZovu44wz8d0XyD1kq0Imao4Ypow5+3CL7CDs2X/wCamRK6AiT9yZwoTiWaop07D7Dr1q0KCTW5kJuyV1YLlcC9JUZBcdyMwjVjua53TzkVxl X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(7416014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Jul 2024 15:09:45.3371 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2431b0ee-0c4d-4678-e36d-08dcb172d009 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4137 When Secure TSC is enabled and TscInvariant (bit 8) in CPUID_8000_0007_edx is set, the kernel complains with the below firmware bug: [Firmware Bug]: TSC doesn't count with P0 frequency! Secure TSC does not need to run at P0 frequency; the TSC frequency is set by the VMM as part of the SNP_LAUNCH_START command. Skip this check when Secure TSC is enabled Signed-off-by: Nikunj A Dadhania Tested-by: Peter Gonda Reviewed-by: Tom Lendacky --- arch/x86/kernel/cpu/amd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index be5889bded49..87b55d2183a0 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -370,7 +370,8 @@ static void bsp_determine_snp(struct cpuinfo_x86 *c) static void bsp_init_amd(struct cpuinfo_x86 *c) { - if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { + if (cpu_has(c, X86_FEATURE_CONSTANT_TSC) && + !cc_platform_has(CC_ATTR_GUEST_SECURE_TSC)) { if (c->x86 > 0x10 || (c->x86 == 0x10 && c->x86_model >= 0x2)) {