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b=LpfInkhKQ1oLO/q5g38cLHYKh8MgAlKVqvF1LM8+L1p+f5Dfee5K7nmE8bqdw6V/po FmdTzQ1rVkMwoL92lssXwnAbnUzSbcLiW+iPS7+fUWmd+MAV2PsFEbG6IVfoK/TqGJt6 Do2lYrd0F5vfI5CIc14/tJQpW9sLhH2ToSW2M7e8dziasAlJr2Qf2gs8so3jzsB1cTYI WOQzRz0huBxizqTIdeWxMxuwFTN38i/WWAGInf5vgoqI0w8LpBY56Hjxdg4j+kEGtnFB kMz0bOr50GfP1Q+U7wNDKip3nFEfGPunGOpYkIY9zPPbO9gJR19YJM2QJhU4Eew6nDLJ mQRw== X-Forwarded-Encrypted: i=1; AJvYcCWXCie4YVnDg5RDLclO8vRdnOeL3pGkgwENyKhFC+w8CAv38gQ+GfIWSRq+FjuWDaHlNWKz4Zm69bffklUKryPyXv1r X-Gm-Message-State: AOJu0Yxdn27HW2RaNGUwEHXGuLAobceoKaN+wYdie49UoAJaSPv0hohs 6WvhW6pn5mk6dKVmId80ZD/EDokjunqhUbuLJzzsMRMxnO/Yu0Xny4o9sBk0HKW58D3tMxceihX Q0cRQrA== X-Google-Smtp-Source: AGHT+IGgJu42eibEXwGmvhNIKvCVPcTIrKdXusvwGwzjhiPGFNmYBNNMkSLWK0IiHmwfzRGjr6PPwL6r9sPb X-Received: from mizhang-super.c.googlers.com ([35.247.89.60]) (user=mizhang job=sendgmr) by 2002:a17:902:c40a:b0:1fc:6c23:8a69 with SMTP id d9443c01a7336-1ff4d1ffd30mr929935ad.7.1722488382211; Wed, 31 Jul 2024 21:59:42 -0700 (PDT) Reply-To: Mingwei Zhang Date: Thu, 1 Aug 2024 04:58:26 +0000 In-Reply-To: <20240801045907.4010984-1-mizhang@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240801045907.4010984-1-mizhang@google.com> X-Mailer: git-send-email 2.46.0.rc1.232.g9752f9e123-goog Message-ID: <20240801045907.4010984-18-mizhang@google.com> Subject: [RFC PATCH v3 17/58] perf: core/x86: Plumb passthrough PMU capability from x86_pmu to x86_pmu_cap From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , Mingwei Zhang , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , Like Xu , Peter Zijlstra , Raghavendra Rao Ananta , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org Plumb passthrough PMU capability to x86_pmu_cap in order to let any kernel entity such as KVM know that host PMU support passthrough PMU mode and has the implementation. Signed-off-by: Mingwei Zhang Signed-off-by: Dapeng Mi Tested-by: Yongwei Ma --- arch/x86/events/core.c | 1 + arch/x86/include/asm/perf_event.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index cb5d8f5fd9ce..c16ceebf2d70 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -3029,6 +3029,7 @@ void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) cap->events_mask = (unsigned int)x86_pmu.events_maskl; cap->events_mask_len = x86_pmu.events_mask_len; cap->pebs_ept = x86_pmu.pebs_ept; + cap->passthrough = !!(pmu.capabilities & PERF_PMU_CAP_PASSTHROUGH_VPMU); } EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 7f1e17250546..5cf37fe1f30a 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -258,6 +258,7 @@ struct x86_pmu_capability { unsigned int events_mask; int events_mask_len; unsigned int pebs_ept :1; + unsigned int passthrough :1; }; /*