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b=pEg6v6CnymMxpw/dvj47hi2aGTMUbasNyl1jSeA+995tJyjNX5iKZPIfG+Oi+eRtbZ hvzaDX7NlNJJIsgGriO0X5659uRLr3QN57DNuLdzXZN/oDN25f2LyzcUH1xRHzv9zk3X aZABrnIBZGkeEjYFc5GvP7I7BP9gYhWaSWRaIm1fIRNL+u633hVdCTkVdh6As37BZ3dW TodEPLyKIsMUuHjsGWRVOH7lGs51hDyXhPzg7wOb2WEdsAmPoFHaZzTPqOOh0x4BziT3 WUreiK886nfO4e/5BIxIonGR95T2YlYhgaGC0uTwOnFEa0hzAbBEb9zMLqs1y5Kpoij/ jyMw== X-Forwarded-Encrypted: i=1; AJvYcCXTsCv/GuqhRL8rRyQTdnSbnC2XW6cbeotIC1km8c3if3Fob6dXcDCBAaYtJvPuUVoOTq6OTKe9A8L5ueU7faYT8ji1 X-Gm-Message-State: AOJu0YzUQ82TVpZQ+W6hUoYmat3DC3RPyAagERwvSw0VuDUhRg0W60Mj OaI/VqLz7HN7UgNuFrd94VvGCqPv8++T3CPLEX13azxs7DyrfSTPhy4tsp6kqZVqbBL/WptT22O bgucaWQ== X-Google-Smtp-Source: AGHT+IFTMAmfGnGK0igFx7Zv5FKwA/uTx54JxyxM0/4jv+JbOdblOvarmWsJVgiS5TVGU8XxieB3hR4Wn3IC X-Received: from mizhang-super.c.googlers.com ([34.105.13.176]) (user=mizhang job=sendgmr) by 2002:a17:902:788c:b0:1fd:6529:7443 with SMTP id d9443c01a7336-1ff4d241368mr467005ad.11.1722488429024; Wed, 31 Jul 2024 22:00:29 -0700 (PDT) Reply-To: Mingwei Zhang Date: Thu, 1 Aug 2024 04:58:51 +0000 In-Reply-To: <20240801045907.4010984-1-mizhang@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240801045907.4010984-1-mizhang@google.com> X-Mailer: git-send-email 2.46.0.rc1.232.g9752f9e123-goog Message-ID: <20240801045907.4010984-43-mizhang@google.com> Subject: [RFC PATCH v3 42/58] KVM: x86/pmu: Introduce PMU operator to increment counter From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , Mingwei Zhang , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , Like Xu , Peter Zijlstra , Raghavendra Rao Ananta , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org Introduce PMU operator to increment counter because in passthrough PMU there is no common backend implementation like host perf API. Having a PMU operator for counter increment and overflow checking will help hiding architectural differences. So Introduce the operator function to make it convenient for passthrough PMU to synthesize a PMI. Signed-off-by: Mingwei Zhang Signed-off-by: Dapeng Mi --- arch/x86/include/asm/kvm-x86-pmu-ops.h | 1 + arch/x86/kvm/pmu.h | 1 + arch/x86/kvm/vmx/pmu_intel.c | 12 ++++++++++++ 3 files changed, 14 insertions(+) diff --git a/arch/x86/include/asm/kvm-x86-pmu-ops.h b/arch/x86/include/asm/kvm-x86-pmu-ops.h index 1a848ba6a7a7..72ca78df8d2b 100644 --- a/arch/x86/include/asm/kvm-x86-pmu-ops.h +++ b/arch/x86/include/asm/kvm-x86-pmu-ops.h @@ -27,6 +27,7 @@ KVM_X86_PMU_OP_OPTIONAL(cleanup) KVM_X86_PMU_OP_OPTIONAL(passthrough_pmu_msrs) KVM_X86_PMU_OP_OPTIONAL(save_pmu_context) KVM_X86_PMU_OP_OPTIONAL(restore_pmu_context) +KVM_X86_PMU_OP_OPTIONAL(incr_counter) #undef KVM_X86_PMU_OP #undef KVM_X86_PMU_OP_OPTIONAL diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 9cde62f3988e..325f17673a00 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -44,6 +44,7 @@ struct kvm_pmu_ops { void (*passthrough_pmu_msrs)(struct kvm_vcpu *vcpu); void (*save_pmu_context)(struct kvm_vcpu *vcpu); void (*restore_pmu_context)(struct kvm_vcpu *vcpu); + bool (*incr_counter)(struct kvm_pmc *pmc); const u64 EVENTSEL_EVENT; const int MAX_NR_GP_COUNTERS; diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 40c503cd263b..42af2404bdb9 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -74,6 +74,17 @@ static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data) } } +static bool intel_incr_counter(struct kvm_pmc *pmc) +{ + pmc->counter += 1; + pmc->counter &= pmc_bitmask(pmc); + + if (!pmc->counter) + return true; + + return false; +} + static struct kvm_pmc *intel_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu, unsigned int idx, u64 *mask) { @@ -885,6 +896,7 @@ struct kvm_pmu_ops intel_pmu_ops __initdata = { .passthrough_pmu_msrs = intel_passthrough_pmu_msrs, .save_pmu_context = intel_save_guest_pmu_context, .restore_pmu_context = intel_restore_guest_pmu_context, + .incr_counter = intel_incr_counter, .EVENTSEL_EVENT = ARCH_PERFMON_EVENTSEL_EVENT, .MAX_NR_GP_COUNTERS = KVM_INTEL_PMC_MAX_GENERIC, .MIN_NR_GP_COUNTERS = 1,