diff mbox series

[RFC,4/5] KVM: SVM: Prevent writes to TSC MSR when Secure TSC is enabled

Message ID 20240829053748.8283-5-nikunj@amd.com (mailing list archive)
State New, archived
Headers show
Series Enable Secure TSC for SEV-SNP | expand

Commit Message

Nikunj A. Dadhania Aug. 29, 2024, 5:37 a.m. UTC 
For a Secure TSC enabled SNP guest, writes to MSR_IA32_TSC is not expected.
Log the error and return #GP.

Signed-off-by: Nikunj A Dadhania <nikunj@amd.com>
---
 arch/x86/kvm/svm/svm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)
diff mbox series

Patch

diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index bf86410b2f43..f9b2c1956a60 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -3151,6 +3151,17 @@  static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
 
 		svm->tsc_aux = data;
 		break;
+	case MSR_IA32_TSC:
+		/*
+		 * If Secure TSC is enabled, KVM doesn't expect to receive
+		 * a VMEXIT for a TSC write, record the error and return a
+		 * #GP
+		 */
+		if (vcpu->arch.guest_state_protected && snp_secure_tsc_enabled(vcpu->kvm)) {
+			vcpu_unimpl(vcpu, "unimplemented IA32_TSC for secure tsc\n");
+			return 1;
+		}
+		break;
 	case MSR_IA32_DEBUGCTLMSR:
 		if (!lbrv) {
 			kvm_pr_unimpl_wrmsr(vcpu, ecx, data);