From patchwork Tue Sep 3 15:38:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13788956 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EC54188917; Tue, 3 Sep 2024 15:38:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725377921; cv=none; b=BDyw2kO/7iaATmD7+YKjh3q63JALHJDszaVlyVwbO7lT6dweJHnfL+n7yI4m6gEBvMu1DV6Bij2cmO6aIBFnh2PRNkVqxUnrHVqhz1o2Tj/saDbblERjggq/iEIcD+o4+Prw9jGwSIpmlf6tMzDyl63Po7etmff79Ttw4p4eWSQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725377921; c=relaxed/simple; bh=Ng2pK8JAkvz2K6GuyrJR7f15eF6wu10+HCeZfrj8mgg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fM09WM8rvDq5mHprLy8ts011z6CtpViql14GUYVi4PLy4rKIuTn9YdEwAgCBfvLYRh+2M3ltkIOR+vGAfIVaRKXS0UmEhjWmX2Bv2WRcM6JW0sk4KiOoMVeMZXKHGqs4Y/I758BigNQff+1SEvo6ov4vEi8kKGqdb81MWvtmui4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Np3wH8Bb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Np3wH8Bb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2BDFFC4CECD; Tue, 3 Sep 2024 15:38:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725377921; bh=Ng2pK8JAkvz2K6GuyrJR7f15eF6wu10+HCeZfrj8mgg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Np3wH8BbGCNjg04omdVfaSllxiYXMAlN6F/nKBq54rzvyLEdomUWk19ZGNFEffDDc j9iGA89tWE5cS5BqHowpOmV0oZXr3PLWMEkD5QXaAR4w16DfjKbQ5oVxcVT/E9SXeA PsJtwfIv7VipvLBzcc4/STjc33CtRtlQfExG4H7aThA0X7AIrEb4ySSRdocKb+jtIW 6XcFSKdbyNohBW3YJtyN1KSTxcsnt0sS++xhn823O6+hlTf652PJQGoj8wX7zmSxQw 45EO8JS5P2DqXmRgOGU+QAaeFvmWvX0F3YCIzrUHrbB82Ba8KgaGMZhTgOtEjtwfY1 1G2HswxGgOGSg== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1slVc7-009Hr9-3T; Tue, 03 Sep 2024 16:38:39 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly , Alexandru Elisei , Mark Brown Subject: [PATCH v2 03/16] KVM: arm64: Add TCR2_EL2 to the sysreg arrays Date: Tue, 3 Sep 2024 16:38:21 +0100 Message-Id: <20240903153834.1909472-4-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240903153834.1909472-1-maz@kernel.org> References: <20240903153834.1909472-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, joey.gouly@arm.com, alexandru.elisei@arm.com, broonie@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Add the TCR2_EL2 register to the per-vcpu sysreg register array, as well as the sysreg descriptor array. Access to this register is conditional based on ID_AA64MMFR3_EL1.TCRX being advertised. Reviewed-by: Joey Gouly Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/sys_regs.c | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index a33f5996ca9f..5a9e0ad35580 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -462,6 +462,7 @@ enum vcpu_sysreg { TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ TCR_EL2, /* Translation Control Register (EL2) */ + TCR2_EL2, /* Extended Translation Control Register (EL2) */ SPSR_EL2, /* EL2 saved program status register */ ELR_EL2, /* EL2 exception link register */ AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 7563826f286a..0510e96f732a 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -436,6 +436,18 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu, return true; } +static bool access_tcr2_el2(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, TCRX, IMP)) { + kvm_inject_undefined(vcpu); + return false; + } + + return access_rw(vcpu, p, r); +} + static bool access_actlr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -2783,6 +2795,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), + EL2_REG(TCR2_EL2, access_tcr2_el2, reset_val, TCR2_EL2_RES1), EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), EL2_REG_VNCR(VTCR_EL2, reset_val, 0),