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Sat, 7 Sep 2024 06:17:08 -0400 (EDT) From: Jiaxun Yang Date: Sat, 07 Sep 2024 11:17:03 +0100 Subject: [PATCH 1/5] LoongArch: Rename cpu_has_csr as cpu_has_iocsr Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240907-iocsr-v1-1-0c99b3334444@flygoat.com> References: <20240907-iocsr-v1-0-0c99b3334444@flygoat.com> In-Reply-To: <20240907-iocsr-v1-0-0c99b3334444@flygoat.com> To: Huacai Chen , WANG Xuerui , "Rafael J. Wysocki" , Viresh Kumar , Thomas Gleixner , Thomas Bogendoerfer Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mips@vger.kernel.org, kvm@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2334; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=wNTWbaQ3JwwfsBAMFy/hbQ4QwVJklrQxDjLfp0v17+I=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrQ7GkpTdvr/Phjcp7IvsXXKlsMMZ6+01e5Oqwmp+3825 Mwr9TNTOkpZGMS4GGTFFFlCBJT6NjReXHD9QdYfmDmsTCBDGLg4BWAiEj0M/531r/zcvdvmwtOn V+6+WhZ9qrg1Zs7eB7dW2Dzad2Pi98q7DP+zUivDDv8R1Y9lu3ItrU3pi9Y3znUcW+6XxpQtk73 4rZgHAA== X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 It meant to be IOCSR as CSR is not optional for LoongArch. Signed-off-by: Jiaxun Yang --- arch/loongarch/include/asm/cpu-features.h | 2 +- arch/loongarch/include/asm/cpu.h | 2 +- arch/loongarch/kernel/cpu-probe.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/loongarch/include/asm/cpu-features.h b/arch/loongarch/include/asm/cpu-features.h index 16a716f88a5c..0190ed28a647 100644 --- a/arch/loongarch/include/asm/cpu-features.h +++ b/arch/loongarch/include/asm/cpu-features.h @@ -50,7 +50,7 @@ #define cpu_has_lbt_arm cpu_opt(LOONGARCH_CPU_LBT_ARM) #define cpu_has_lbt_mips cpu_opt(LOONGARCH_CPU_LBT_MIPS) #define cpu_has_lbt (cpu_has_lbt_x86|cpu_has_lbt_arm|cpu_has_lbt_mips) -#define cpu_has_csr cpu_opt(LOONGARCH_CPU_CSR) +#define cpu_has_iocsr cpu_opt(LOONGARCH_CPU_IOCSR) #define cpu_has_tlb cpu_opt(LOONGARCH_CPU_TLB) #define cpu_has_watch cpu_opt(LOONGARCH_CPU_WATCH) #define cpu_has_vint cpu_opt(LOONGARCH_CPU_VINT) diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/cpu.h index 843f9c4ec980..7c44f4ede3a2 100644 --- a/arch/loongarch/include/asm/cpu.h +++ b/arch/loongarch/include/asm/cpu.h @@ -115,7 +115,7 @@ enum cpu_type_enum { #define LOONGARCH_CPU_LBT_ARM BIT_ULL(CPU_FEATURE_LBT_ARM) #define LOONGARCH_CPU_LBT_MIPS BIT_ULL(CPU_FEATURE_LBT_MIPS) #define LOONGARCH_CPU_TLB BIT_ULL(CPU_FEATURE_TLB) -#define LOONGARCH_CPU_CSR BIT_ULL(CPU_FEATURE_CSR) +#define LOONGARCH_CPU_IOCSR BIT_ULL(CPU_FEATURE_IOCSR) #define LOONGARCH_CPU_WATCH BIT_ULL(CPU_FEATURE_WATCH) #define LOONGARCH_CPU_VINT BIT_ULL(CPU_FEATURE_VINT) #define LOONGARCH_CPU_CSRIPI BIT_ULL(CPU_FEATURE_CSRIPI) diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-probe.c index 14f0449f5452..4446616d497c 100644 --- a/arch/loongarch/kernel/cpu-probe.c +++ b/arch/loongarch/kernel/cpu-probe.c @@ -91,7 +91,7 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c) unsigned int config; unsigned long asid_mask; - c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_CSR | + c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_IOCSR | LOONGARCH_CPU_TLB | LOONGARCH_CPU_VINT | LOONGARCH_CPU_WATCH; elf_hwcap = HWCAP_LOONGARCH_CPUCFG;