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Sat, 7 Sep 2024 06:17:10 -0400 (EDT) From: Jiaxun Yang Date: Sat, 07 Sep 2024 11:17:04 +0100 Subject: [PATCH 2/5] LoongArch: Probe more CPU features from CPUCFG Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240907-iocsr-v1-2-0c99b3334444@flygoat.com> References: <20240907-iocsr-v1-0-0c99b3334444@flygoat.com> In-Reply-To: <20240907-iocsr-v1-0-0c99b3334444@flygoat.com> To: Huacai Chen , WANG Xuerui , "Rafael J. Wysocki" , Viresh Kumar , Thomas Gleixner , Thomas Bogendoerfer Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mips@vger.kernel.org, kvm@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4645; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=dGuxM8PZ+MkpKKAh5LWup1ti6kx4IwMUcMWFV7XToMY=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrQ7GkqmCz2jHJz9OBTndJn0lvxZ5drxo7fJYdUs8W929 gKTfj7qKGVhEONikBVTZAkRUOrb0HhxwfUHWX9g5rAygQxh4OIUgImwMTL8zz+yQW3asld6b7kP 1H+ZvC7+xsRnc27vap+8aOGsP3PnBD9jZHg/0SmIadtObqZ/s5LktK5ea+eWONr5ksGXxeG4os/ 8LawA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Probe ISA level, TLB, IOCSR information from CPUCFG to improve kernel resilience to different core implementations. Signed-off-by: Jiaxun Yang --- arch/loongarch/include/asm/cpu.h | 2 +- arch/loongarch/kernel/cpu-probe.c | 47 ++++++++++++++++++++++++++------------- 2 files changed, 32 insertions(+), 17 deletions(-) diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/cpu.h index 7c44f4ede3a2..31a2de821236 100644 --- a/arch/loongarch/include/asm/cpu.h +++ b/arch/loongarch/include/asm/cpu.h @@ -86,7 +86,7 @@ enum cpu_type_enum { #define CPU_FEATURE_LBT_ARM 11 /* CPU has ARM Binary Translation */ #define CPU_FEATURE_LBT_MIPS 12 /* CPU has MIPS Binary Translation */ #define CPU_FEATURE_TLB 13 /* CPU has TLB */ -#define CPU_FEATURE_CSR 14 /* CPU has CSR */ +#define CPU_FEATURE_IOCSR 14 /* CPU has IOCSR */ #define CPU_FEATURE_WATCH 15 /* CPU has watchpoint registers */ #define CPU_FEATURE_VINT 16 /* CPU has vectored interrupts */ #define CPU_FEATURE_CSRIPI 17 /* CPU has CSR-IPI */ diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-probe.c index 4446616d497c..6a82ceb6e321 100644 --- a/arch/loongarch/kernel/cpu-probe.c +++ b/arch/loongarch/kernel/cpu-probe.c @@ -91,12 +91,23 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c) unsigned int config; unsigned long asid_mask; - c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_IOCSR | - LOONGARCH_CPU_TLB | LOONGARCH_CPU_VINT | LOONGARCH_CPU_WATCH; + c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_VINT | + LOONGARCH_CPU_WATCH; elf_hwcap = HWCAP_LOONGARCH_CPUCFG; config = read_cpucfg(LOONGARCH_CPUCFG1); + + if (config & CPUCFG1_ISGR64) + set_isa(c, LOONGARCH_CPU_ISA_LA64); + else if (config & CPUCFG1_ISGR32) + set_isa(c, LOONGARCH_CPU_ISA_LA32S); + else + set_isa(c, LOONGARCH_CPU_ISA_LA32R); + if (config & CPUCFG1_PAGING) + c->options |= LOONGARCH_CPU_TLB; + if (config & CPUCFG1_IOCSR) + c->options |= LOONGARCH_CPU_IOCSR; if (config & CPUCFG1_UAL) { c->options |= LOONGARCH_CPU_UAL; elf_hwcap |= HWCAP_LOONGARCH_UAL; @@ -222,6 +233,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_loongarch *c, unsigned int { uint64_t *vendor = (void *)(&cpu_full_name[VENDOR_OFFSET]); uint64_t *cpuname = (void *)(&cpu_full_name[CPUNAME_OFFSET]); + const char *core_name = "Unknown"; if (!__cpu_full_name[cpu]) __cpu_full_name[cpu] = cpu_full_name; @@ -232,40 +244,43 @@ static inline void cpu_probe_loongson(struct cpuinfo_loongarch *c, unsigned int switch (c->processor_id & PRID_SERIES_MASK) { case PRID_SERIES_LA132: c->cputype = CPU_LOONGSON32; - set_isa(c, LOONGARCH_CPU_ISA_LA32S); __cpu_family[cpu] = "Loongson-32bit"; - pr_info("32-bit Loongson Processor probed (LA132 Core)\n"); + core_name = "LA132"; break; case PRID_SERIES_LA264: c->cputype = CPU_LOONGSON64; - set_isa(c, LOONGARCH_CPU_ISA_LA64); __cpu_family[cpu] = "Loongson-64bit"; - pr_info("64-bit Loongson Processor probed (LA264 Core)\n"); + core_name = "LA264"; break; case PRID_SERIES_LA364: c->cputype = CPU_LOONGSON64; - set_isa(c, LOONGARCH_CPU_ISA_LA64); __cpu_family[cpu] = "Loongson-64bit"; - pr_info("64-bit Loongson Processor probed (LA364 Core)\n"); + core_name = "LA364"; break; case PRID_SERIES_LA464: c->cputype = CPU_LOONGSON64; - set_isa(c, LOONGARCH_CPU_ISA_LA64); __cpu_family[cpu] = "Loongson-64bit"; - pr_info("64-bit Loongson Processor probed (LA464 Core)\n"); + core_name = "LA464"; break; case PRID_SERIES_LA664: c->cputype = CPU_LOONGSON64; - set_isa(c, LOONGARCH_CPU_ISA_LA64); __cpu_family[cpu] = "Loongson-64bit"; - pr_info("64-bit Loongson Processor probed (LA664 Core)\n"); + core_name = "LA664"; break; default: /* Default to 64 bit */ - c->cputype = CPU_LOONGSON64; - set_isa(c, LOONGARCH_CPU_ISA_LA64); - __cpu_family[cpu] = "Loongson-64bit"; - pr_info("64-bit Loongson Processor probed (Unknown Core)\n"); + if (c->isa_level & LOONGARCH_CPU_ISA_LA64) { + c->cputype = CPU_LOONGSON64; + __cpu_family[cpu] = "Loongson-64bit"; + } else if (c->isa_level & LOONGARCH_CPU_ISA_LA32S) { + c->cputype = CPU_LOONGSON32; + __cpu_family[cpu] = "Loongson-32bit"; + } else if (c->isa_level & LOONGARCH_CPU_ISA_LA32R) { + c->cputype = CPU_LOONGSON32; + __cpu_family[cpu] = "Loongson-32bit Reduced"; + } } + + pr_info("%s Processor probed (%s Core)\n", __cpu_family[cpu], core_name); } #ifdef CONFIG_64BIT