From patchwork Sun Sep 8 12:59:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13795446 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA656158207 for ; Sun, 8 Sep 2024 12:43:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725799441; cv=none; b=IcY/eEpYaVUY3z98vcDMv9lxOE8cdW7K0627J+X5MoK9nsPEf5sGikrdhsKylRWktemX49WTstqvOkQuY7hydi+mRMyLqN//o3b7k8ytffnkJirsX6Q3orArzybblN2wRXfh66lrjUps3DSJMf+DAbTGE2JjS3EpJVpULWfHM3w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725799441; c=relaxed/simple; bh=BrZawMnp3PVtM7q2OTGYiNtV3fjACaeKSFuVHbGDiaQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dfYw9PZWYtgKExIQGXr+xeGdnDetKV7Ho4rHEcpPpNWfnOi3ndciyVkqfOiPDCG8IUM/MQtaEPEuze+1axSnsa10OXJqEkJeQDivSSaFZj6Y+DFmBHyLZa33tegQrlv08NEXV1ys4JLN9hoB6x616lnWpGmS8vUJTGdkvYb+kvk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=iEQSXrZr; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="iEQSXrZr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725799440; x=1757335440; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BrZawMnp3PVtM7q2OTGYiNtV3fjACaeKSFuVHbGDiaQ=; b=iEQSXrZr4Z02ti94myYHfcoIW8NpX/4jGAFrvDqvk6aHBhox8dqnZEbe DL3cYkGAmRzFfvYg9oji0yzyWxo8r2tMKI+iIcsEHFxwD9XthqfIVEMi+ cw18ImkZ5TrvMpNnCiWm4AwzIXg/javrI6KA8zCmkRIpx5GUk3hbBkJza zkfyI52ILkG5Km0LWIzf/9dHGOtLDpZh6jrQWR5bro9kRpcHFflB2EGs8 qc2COD/gVXp8hzDJKLpWYTM+Fj4AiQCeNYhEhU41LdEoKLGLAw2QZgw68 fccflKHgqCEuxddQZRDKS8s2AB2mct0KOz/l0beAyQq63GPLUtPftlZQh A==; X-CSE-ConnectionGUID: 2fMwo6l8TZ6VYK65j80m6Q== X-CSE-MsgGUID: j8wBrIQ8Rui91nlImbsWPw== X-IronPort-AV: E=McAfee;i="6700,10204,11189"; a="28238237" X-IronPort-AV: E=Sophos;i="6.10,212,1719903600"; d="scan'208";a="28238237" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2024 05:44:00 -0700 X-CSE-ConnectionGUID: WDHpijXHQzaJkHt2SmF1yQ== X-CSE-MsgGUID: e9ixptPWRbKmrxsLHzpRhA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,212,1719903600"; d="scan'208";a="97196648" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa001.fm.intel.com with ESMTP; 08 Sep 2024 05:43:54 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH v2 6/7] i386/cpu: Update cache topology with machine's configuration Date: Sun, 8 Sep 2024 20:59:19 +0800 Message-Id: <20240908125920.1160236-7-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240908125920.1160236-1-zhao1.liu@intel.com> References: <20240908125920.1160236-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User will configure smp cache topology via -machine smp-cache. For this case, update the x86 CPUs' cache topology with user's configuration in MachineState. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma --- Changes since RFC v2: * Used smp_cache array to override cache topology. * Wrapped the updating into a function. --- target/i386/cpu.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e9f755000356..6d9f7dc0872a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7597,6 +7597,38 @@ static void x86_cpu_hyperv_realize(X86CPU *cpu) cpu->hyperv_limits[2] = 0; } +#ifndef CONFIG_USER_ONLY +static void x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu) +{ + CPUX86State *env = &cpu->env; + CpuTopologyLevel level; + + level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); + if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l1d_cache->share_level = level; + env->cache_info_amd.l1d_cache->share_level = level; + } + + level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); + if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l1i_cache->share_level = level; + env->cache_info_amd.l1i_cache->share_level = level; + } + + level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); + if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l2_cache->share_level = level; + env->cache_info_amd.l2_cache->share_level = level; + } + + level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); + if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l3_cache->share_level = level; + env->cache_info_amd.l3_cache->share_level = level; + } +} +#endif + static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -7821,6 +7853,13 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) #ifndef CONFIG_USER_ONLY MachineState *ms = MACHINE(qdev_get_machine()); + + /* + * TODO: Add a SMPCompatProps.has_caches flag to avoid useless Updates + * if user didn't set smp_cache. + */ + x86_cpu_update_smp_cache_topo(ms, cpu); + qemu_register_reset(x86_cpu_machine_reset_cb, cpu); if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {