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Fri, 20 Sep 2024 15:35:01 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , Subject: [RFC 09/13] vfio/pci: introduce CXL device awareness Date: Fri, 20 Sep 2024 15:34:42 -0700 Message-ID: <20240920223446.1908673-10-zhiw@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240920223446.1908673-1-zhiw@nvidia.com> References: <20240920223446.1908673-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D2:EE_|PH8PR12MB7230:EE_ X-MS-Office365-Filtering-Correlation-Id: 2f319e89-6e3f-4cd8-1080-08dcd9c47f1d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: jPI6YGLcRnzcp9C8LMhCwT0e0F+ZUw86Z+sweCLwuzZsN5zrA2moqVyF6B9nDM9gy/sNe3yjUaB9ro1mSMfCb0BJvhEDbKLqwhmmkROEStFB4IA5JVJEkNyU4zANatHjajnUaHag7xGQuJnG6V8dTbk6dHgms3l/s+N3vl0og1qw4Yj9D5qzqh9oZYar/Vi3xsOcXPHHEBagRq7wtOlwtnw+7YLA3UTmsR5L07l+PEKAtGCDhsaaSixXycGZVUpn9RGOi0uWJNUPZQY5o9sfHWpO83RWC9uXPj2yyowBPWBIkMc8aFZ4J0t8SJUqR48ov+Lntwo50xBbRg3JlU/nPjf1cAPEJIdISGU+Ek2z7tBKzrfAj40WHkemkdId3q9jIpPXUBHVbFsh+oPI2JpjNOgYcZk/iHlwsn6RYaK18c6yy0l/NJwEZT74Zi899rrB9GgzY+yDLzDmvjPv7dYUm7UMFa1Oa0EVmWGQV11bpcBe5ENOb1JsFj0Gkijga0OAl8PyPyxrsYyaP7Nt8fk/FqTchfL/ngsS8dBYkOuohBjJrFCvFnJNBxt94bh2K5aPyZdMSKiGje8//QIad6XufwYEvfURDzMJaaZ5EYzycRkFdL31NM3evq3sYnYYEWIWxY9SU5Vwe2Akyh1G7kn/GMX0HQQfaYxXqW5XVETCMkRHTeH4hySol7uuAFrK87GjFmH7QSKYFp1yt39JG1dIG1HGNTbMI4U4KbAAE++LhDPz9840Iyb0n8/GwvGodIJ96qa+inAqrT5wqchiha+/KhTexjBbMCUIy3d9SdbrUZm61jwAQJmjkhOcFSpcibQ54dY8CuZHeWdN708ggxbMfosG+tRVfzETJiopvagnYIpk2+Jb8HXcrhdx5ZXXheL53ZsxC1i01+S6AarYTYbgh/v+pDV2N7u24x8QDh7kI9cokmKM4a8TGiCBK1Qznog16BrzOTYXlckJsHq/wdjeNss7NII6ZQk45QoaCxbbfh2Yvcb3gU5/38t6AGXP66McmugylXsO9hj0ZUPOmbjpooIsv010mvjK1Uos4sN8CnoBF6axFWelOmJK216HIVHKJxFJp/WvOjNjXwTrBZSUkUGHAcoCwvQom+F0CjHTsMQgYk/Wu0Q+v6FkP7UR86VOReBnpT14pSVpq1vlRbgCbCwHDZz+uYePYi361QiHhA/lA7XYrJXbdPwj6gaB8mv0rR2bi4akZe/fc/dtjsRMNAZXOCPq5eupNd4l3kh12N96zCyHTodgW5TBpao44pEvd44w6WMRBLu/hF2pyM3mX+lwZ7u6XHlG7rKK12BCpWqKLhZXKGr3dFras5vUOWmu2V3PJqgJc5ZojhRO4HuQLgXhwhvNUggRtmDcNh5v3V1BVFOY2lxVkb1iqnztV1Su7ppzoHXjI+lKVY1tQyFMsJ+9T1qpj16QlmcJfTgEzWehw0Y3yhOLpuapya2R1oua X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:14.7790 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2f319e89-6e3f-4cd8-1080-08dcd9c47f1d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7230 CXL device programming interfaces are built upon PCI interfaces. Thus the vfio-pci-core can be leveraged to handle a CXL device. However, CXL device also has difference with PCI devicce: - No INTX support, only MSI/MSIX is supported. - Resest is one via CXL reset. FLR only resets CXL.io. Introduce the CXL device awareness to the vfio-pci-core. Expose a new VFIO device flags to the userspace to identify the VFIO device is a CXL device. Disable INTX support in the vfio-pci-core. Disable FLR reset for the CXL device as the kernel CXL core hasn't support CXL reset yet. Disable mmap support on the CXL MMIO BAR in vfio-pci-core. Signed-off-by: Zhi Wang --- drivers/vfio/pci/vfio_cxl_core.c | 8 ++++++ drivers/vfio/pci/vfio_pci_core.c | 42 +++++++++++++++++++++----------- include/linux/vfio_pci_core.h | 2 ++ include/uapi/linux/vfio.h | 1 + 4 files changed, 39 insertions(+), 14 deletions(-) diff --git a/drivers/vfio/pci/vfio_cxl_core.c b/drivers/vfio/pci/vfio_cxl_core.c index bbb968cb1b70..d8b51f8792a2 100644 --- a/drivers/vfio/pci/vfio_cxl_core.c +++ b/drivers/vfio/pci/vfio_cxl_core.c @@ -391,6 +391,8 @@ int vfio_cxl_core_enable(struct vfio_pci_core_device *core_dev) if (ret) return ret; + vfio_pci_core_enable_cxl(core_dev); + ret = vfio_pci_core_enable(core_dev); if (ret) goto err_pci_core_enable; @@ -618,6 +620,12 @@ ssize_t vfio_cxl_core_write(struct vfio_device *core_vdev, const char __user *bu } EXPORT_SYMBOL_GPL(vfio_cxl_core_write); +void vfio_pci_core_enable_cxl(struct vfio_pci_core_device *core_dev) +{ + core_dev->has_cxl = true; +} +EXPORT_SYMBOL(vfio_pci_core_enable_cxl); + MODULE_LICENSE("GPL"); MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_DESCRIPTION(DRIVER_DESC); diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index 9373942f1acb..e0f23b538858 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -126,6 +126,9 @@ static void vfio_pci_probe_mmaps(struct vfio_pci_core_device *vdev) if (!(res->flags & IORESOURCE_MEM)) goto no_mmap; + if (vdev->has_cxl && bar == vdev->cxl.comp_reg_bar) + goto no_mmap; + /* * The PCI core shouldn't set up a resource with a * type but zero size. But there may be bugs that @@ -487,10 +490,15 @@ int vfio_pci_core_enable(struct vfio_pci_core_device *vdev) if (ret) goto out_power; - /* If reset fails because of the device lock, fail this path entirely */ - ret = pci_try_reset_function(pdev); - if (ret == -EAGAIN) - goto out_disable_device; + if (!vdev->has_cxl) { + /* If reset fails because of the device lock, fail this path entirely */ + ret = pci_try_reset_function(pdev); + if (ret == -EAGAIN) + goto out_disable_device; + } else { + /* CXL Reset is missing in CXL core. FLR only resets CXL.io path. */ + ret = -ENODEV; + } vdev->reset_works = !ret; pci_save_state(pdev); @@ -498,14 +506,17 @@ int vfio_pci_core_enable(struct vfio_pci_core_device *vdev) if (!vdev->pci_saved_state) pci_dbg(pdev, "%s: Couldn't store saved state\n", __func__); - if (likely(!nointxmask)) { - if (vfio_pci_nointx(pdev)) { - pci_info(pdev, "Masking broken INTx support\n"); - vdev->nointx = true; - pci_intx(pdev, 0); - } else - vdev->pci_2_3 = pci_intx_mask_supported(pdev); - } + if (!vdev->has_cxl) { + if (likely(!nointxmask)) { + if (vfio_pci_nointx(pdev)) { + pci_info(pdev, "Masking broken INTx support\n"); + vdev->nointx = true; + pci_intx(pdev, 0); + } else + vdev->pci_2_3 = pci_intx_mask_supported(pdev); + } + } else + vdev->nointx = true; /* CXL device doesn't have INTX. */ pci_read_config_word(pdev, PCI_COMMAND, &cmd); if (vdev->pci_2_3 && (cmd & PCI_COMMAND_INTX_DISABLE)) { @@ -541,7 +552,6 @@ int vfio_pci_core_enable(struct vfio_pci_core_device *vdev) if (!vfio_vga_disabled() && vfio_pci_is_vga(pdev)) vdev->has_vga = true; - return 0; out_free_zdev: @@ -657,7 +667,8 @@ void vfio_pci_core_disable(struct vfio_pci_core_device *vdev) * Disable INTx and MSI, presumably to avoid spurious interrupts * during reset. Stolen from pci_reset_function() */ - pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); + if (!vdev->nointx) + pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); /* * Try to get the locks ourselves to prevent a deadlock. The @@ -973,6 +984,9 @@ static int vfio_pci_ioctl_get_info(struct vfio_pci_core_device *vdev, if (vdev->reset_works) info.flags |= VFIO_DEVICE_FLAGS_RESET; + if (vdev->has_cxl) + info.flags |= VFIO_DEVICE_FLAGS_CXL; + info.num_regions = VFIO_PCI_NUM_REGIONS + vdev->num_regions; info.num_irqs = VFIO_PCI_NUM_IRQS; diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index 9d295ca9382a..e5646aad3eb3 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -113,6 +113,7 @@ struct vfio_pci_core_device { bool needs_pm_restore:1; bool pm_intx_masked:1; bool pm_runtime_engaged:1; + bool has_cxl:1; struct pci_saved_state *pci_saved_state; struct pci_saved_state *pm_save; int ioeventfds_nr; @@ -208,5 +209,6 @@ ssize_t vfio_cxl_core_read(struct vfio_device *core_vdev, char __user *buf, size_t count, loff_t *ppos); ssize_t vfio_cxl_core_write(struct vfio_device *core_vdev, const char __user *buf, size_t count, loff_t *ppos); +void vfio_pci_core_enable_cxl(struct vfio_pci_core_device *core_dev); #endif /* VFIO_PCI_CORE_H */ diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 71f766c29060..0895183feaac 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -214,6 +214,7 @@ struct vfio_device_info { #define VFIO_DEVICE_FLAGS_FSL_MC (1 << 6) /* vfio-fsl-mc device */ #define VFIO_DEVICE_FLAGS_CAPS (1 << 7) /* Info supports caps */ #define VFIO_DEVICE_FLAGS_CDX (1 << 8) /* vfio-cdx device */ +#define VFIO_DEVICE_FLAGS_CXL (1 << 9) /* Device supports CXL support */ __u32 num_regions; /* Max region index + 1 */ __u32 num_irqs; /* Max IRQ index + 1 */ __u32 cap_offset; /* Offset within info struct of first cap */