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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL02EPF00021F6C.mail.protection.outlook.com (10.167.249.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 09:30:02 +0000 Received: from gomati.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 9 Oct 2024 04:29:58 -0500 From: Nikunj A Dadhania To: , , , , CC: , , , , , , Subject: [PATCH v12 14/19] tsc: Use the GUEST_TSC_FREQ MSR for discovering TSC frequency Date: Wed, 9 Oct 2024 14:58:45 +0530 Message-ID: <20241009092850.197575-15-nikunj@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241009092850.197575-1-nikunj@amd.com> References: <20241009092850.197575-1-nikunj@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6C:EE_|PH7PR12MB5617:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b13cfb7-f455-4cae-9e2e-08dce844f41a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: ldQkFkknabsdKJaLCDmmKhZSRBbU2x6NqLOqxz138Fapt6v07+Xm34Iwe62hqY+YxJ3ZIuGgdlVlTWjHmnf97MI4MDUerbK7UA3skeS1xmrrxgcrgLVhuHChjkFYdT2JNwrPhc8wz1ACAHr1ErMGuiINmAZq5yEPMmM0qk6natHbCUTVJLA3hPjS6DBM/niWnBElEcnQ9pzyLN9+Gf9LIwKaqP2qp9pdDZ+kDflfJ2yeKF20pC2KnfShe/1ea9/8tGhk49S8RLt1vUyfkU874WkyF+5Lv/yJ3zR3ixfbDHtpRBQy8RoMZ/p+vEnRNutd6fS+rt4VkDCdIcz8cxFJQ09t/ZsyX6qfAbQRZzZIlKRXySBjzHKXWbq9ShYUrWIKjvLEhdm5/Xmcv61jCN6DhRJgr0PRY8/5pao7nH3k6jej0Pqsw/OlkpEERYyI6G+EakOymDw2XPpCQYCvp/9E+12NKwUZHcGlEu0BYbE3WaM7NxiU79vcsP1DbLdcdlDaa3qkRKL8guCWOTtl0Gj2L0EJE0xIW2tHr8u7SzDE1CCQPPMaka1arO9agQ0TaBfk9lvstfv9L3tY1t5ajfhmW0Af44u+zHe20f34wNTzg3YRBB/JmVdHxFNzntlu3HnEfeVtDgO0od47mTLrD5YtMd/6GFGfftZLh6NgDl+WUu0IX21m8F7631DNsDhL5No2PCH9ST3xxNwLcKTzYQo2bOGElqJn5fzyTZ/Pk82TAo3XqpHgyv8KMLTKZxyQkGT5cLGGhLuV+Bb0vLbw8jblMUnFcYBw7kfA6i15iaOHmXXuOVvtxXrG36F39/PpEthxwxyREbsT5z16Xd2WeQG2hOU2HFGCYOYnZnxiNSEKo3j11qa2rHsVl0yCaLRshZSX0RekFKICJ4Fmthh44J8hgIcGCB5/JEf3+wswFtAEcnlPpS/4TpVI91yiWim8ZWNiCbvnW/RztS3sEFCbeV5geccU0k6u686jBLx0KEaPyHHFUbpnw8DsgJKvDT7ixXL48+Vz32hEXt5zuVo6pybPZ3HBbdjSGk6HvxQZcs+esUobBTp7dIkfOVdSMGXwvU3ejWhR0nNL8JEahrHgaoLf+br2Rf2gwX9QnvEsU4ZZtNHqobSjY1dNKv6JOCU13QAAZfjR/ORlQa7+jvvGz/jhJ42CixM7WggrydlIHZkOEM/9fvyCT5PEsPBPLP0vR/ldx0zlfqgcGXMrOmR/VXjbSSVfBqkvlDepsnZqJArY+9K7xdGQ4wTW7c6IigGoa5fk5apVz3Hkk34pi3Wk7k48S8kXnLtOXAq6F5cUeW9+JJ45KzPxet0ALmNjaiL6D26rG5TbiBxiddQQ8pmBK1cEZgIwWtGSO0OCiGqnwQ8KHAYKkGCf1bLkeQrp11rl3LQa X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 09:30:02.9791 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b13cfb7-f455-4cae-9e2e-08dce844f41a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5617 Calibrating the TSC frequency using the kvmclock is not correct for SecureTSC enabled guests. Use the platform provided TSC frequency via the GUEST_TSC_FREQ MSR (C001_0134h). Signed-off-by: Nikunj A Dadhania --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/sev.h | 2 ++ arch/x86/coco/sev/core.c | 16 ++++++++++++++++ arch/x86/kernel/tsc.c | 5 +++++ 4 files changed, 24 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 3ae84c3b8e6d..233be13cc21f 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -608,6 +608,7 @@ #define MSR_AMD_PERF_CTL 0xc0010062 #define MSR_AMD_PERF_STATUS 0xc0010063 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 +#define MSR_AMD64_GUEST_TSC_FREQ 0xc0010134 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 #define MSR_AMD64_OSVW_STATUS 0xc0010141 #define MSR_AMD_PPIN_CTL 0xc00102f0 diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 9169b18eeb78..34f7b9fc363b 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -536,6 +536,7 @@ static inline int handle_guest_request(struct snp_msg_desc *mdesc, u64 exit_code } void __init snp_secure_tsc_prepare(void); +void __init securetsc_init(void); #else /* !CONFIG_AMD_MEM_ENCRYPT */ @@ -584,6 +585,7 @@ static inline int handle_guest_request(struct snp_msg_desc *mdesc, u64 exit_code u32 resp_sz) { return -ENODEV; } static inline void __init snp_secure_tsc_prepare(void) { } +static inline void __init securetsc_init(void) { } #endif /* CONFIG_AMD_MEM_ENCRYPT */ diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c index 5f555f905fad..ef0def203b3f 100644 --- a/arch/x86/coco/sev/core.c +++ b/arch/x86/coco/sev/core.c @@ -3100,3 +3100,19 @@ void __init snp_secure_tsc_prepare(void) pr_debug("SecureTSC enabled"); } + +static unsigned long securetsc_get_tsc_khz(void) +{ + unsigned long long tsc_freq_mhz; + + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); + rdmsrl(MSR_AMD64_GUEST_TSC_FREQ, tsc_freq_mhz); + + return (unsigned long)(tsc_freq_mhz * 1000); +} + +void __init securetsc_init(void) +{ + x86_platform.calibrate_cpu = securetsc_get_tsc_khz; + x86_platform.calibrate_tsc = securetsc_get_tsc_khz; +} diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index dfe6847fd99e..c83f1091bb4f 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -30,6 +30,7 @@ #include #include #include +#include unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ EXPORT_SYMBOL(cpu_khz); @@ -1514,6 +1515,10 @@ void __init tsc_early_init(void) /* Don't change UV TSC multi-chassis synchronization */ if (is_early_uv_system()) return; + + if (cc_platform_has(CC_ATTR_GUEST_SNP_SECURE_TSC)) + securetsc_init(); + if (!determine_cpu_tsc_frequencies(true)) return; tsc_enable_sched_clock();