From patchwork Sat Oct 12 10:44:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13833911 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4F0A15443C for ; Sat, 12 Oct 2024 10:28:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728728930; cv=none; b=ZvC1MZ7ph5/upWtxa/Hu66B1bMmSNQ8yZ4gb/ANVJQ8pkiGxxIU/pnB+sKgEeAZx81ZYcmTrYa9+765OMvrJlv9C9LET7GeUZ2PL6hwoaIqtfF0y635EF+ENEUWaNa4+9PnXKe8SdMf0n14BfGFolUFsBQ68Lr0zbEO1bUX4Bjg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728728930; c=relaxed/simple; bh=J9p7Tdz/CDqM2wDqm/4H38Zb2VvdiGGpmWwRSF8KKYc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HSzd4OzHcH946H47OYpHIr2gQKYe4o6RbihOaq+dYQsFFFGXu43Vf6lA9tEa5xHWzsOi9mCi7nlmZzooiL6tHkrRKKcLzIP3GjbSiMYruLMaFcevG52uFBjQDtXMIqhBPJvb4dlBmhIsvgxfpuSO297hsxbE/Y7wIxLA6VXQIO4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TgH9/G81; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TgH9/G81" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728728929; x=1760264929; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=J9p7Tdz/CDqM2wDqm/4H38Zb2VvdiGGpmWwRSF8KKYc=; b=TgH9/G818Up0d6CXfhiZiRtcC/3ckDAXoy5Os1yEQeJppmUwKtkzQg+s mChu0g5u2RjbK90atTsINkdpHmcBnNPT53vGuQMbLJYXL57mXrfVdkbT2 tk9rWdNsnjkOsanuguC4tQACXAN8VW/MRbWT8LF5WNK74oR8Tvqdzxp0+ fUdZAklPdDxXa5sgrzA+SC5Z/NT8AI6SEDYXTSrnjRI0VDIgVRXhmnjqp AOYdLjxzbT7h3fmJGyMq2f6RpH1Fz1mAJ12hhWgAsYlP6IVtSDnRNiOwl LbyXEmqJZBNuag0idd1YAS/V+45h9Yqbx64NbfftaIBJOpN+Sd4xN75UH Q==; X-CSE-ConnectionGUID: vkEjZLFwSZKop9fpFX1Z5Q== X-CSE-MsgGUID: e8dyF/QuR0O+bcpYw/nlXg== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="45634884" X-IronPort-AV: E=Sophos;i="6.11,198,1725346800"; d="scan'208";a="45634884" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2024 03:28:49 -0700 X-CSE-ConnectionGUID: 8jua+y5vSJuF4yaj4EUEng== X-CSE-MsgGUID: 7F/JJOcZQjWrB5yLRjPEeQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,198,1725346800"; d="scan'208";a="77050845" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa010.jf.intel.com with ESMTP; 12 Oct 2024 03:28:43 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu , Yongwei Ma Subject: [PATCH v3 3/7] hw/core: Check smp cache topology support for machine Date: Sat, 12 Oct 2024 18:44:25 +0800 Message-Id: <20241012104429.1048908-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241012104429.1048908-1-zhao1.liu@intel.com> References: <20241012104429.1048908-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add cache_supported flags in SMPCompatProps to allow machines to configure various caches support. And check the compatibility of the cache properties with the machine support in machine_parse_smp_cache(). Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v2: * Polished the comment of "default" level check. (Jonathan) * Reduced short line wrap. (Jonathan) Changes since Patch v1: * Dropped machine_check_smp_cache_support() and did the check when -machine parses smp-cache in machine_parse_smp_cache(). Changes since RFC v2: * Split as a separate commit to just include compatibility checking and topology checking. * Allow setting "default" topology level even though the cache isn't supported by machine. (Daniel) --- hw/core/machine-smp.c | 75 +++++++++++++++++++++++++++++++++++++++++++ include/hw/boards.h | 3 ++ 2 files changed, 78 insertions(+) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index 1ce7be902e6e..f3edbded2e7b 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -261,10 +261,47 @@ void machine_parse_smp_config(MachineState *ms, } } +static bool machine_check_topo_support(MachineState *ms, + CpuTopologyLevel topo, + Error **errp) +{ + MachineClass *mc = MACHINE_GET_CLASS(ms); + + if ((topo == CPU_TOPOLOGY_LEVEL_MODULE && !mc->smp_props.modules_supported) || + (topo == CPU_TOPOLOGY_LEVEL_CLUSTER && !mc->smp_props.clusters_supported) || + (topo == CPU_TOPOLOGY_LEVEL_DIE && !mc->smp_props.dies_supported) || + (topo == CPU_TOPOLOGY_LEVEL_BOOK && !mc->smp_props.books_supported) || + (topo == CPU_TOPOLOGY_LEVEL_DRAWER && !mc->smp_props.drawers_supported)) { + error_setg(errp, + "Invalid topology level: %s. " + "The topology level is not supported by this machine", + CpuTopologyLevel_str(topo)); + return false; + } + + return true; +} + +/* + * When both cache1 and cache2 are configured with specific topology levels + * (not default level), is cache1's topology level higher than cache2? + */ +static bool smp_cache_topo_cmp(const SmpCache *smp_cache, + CacheLevelAndType cache1, + CacheLevelAndType cache2) +{ + if (smp_cache->props[cache1].topology != CPU_TOPOLOGY_LEVEL_DEFAULT && + smp_cache->props[cache1].topology > smp_cache->props[cache2].topology) { + return true; + } + return false; +} + bool machine_parse_smp_cache(MachineState *ms, const SmpCachePropertiesList *caches, Error **errp) { + MachineClass *mc = MACHINE_GET_CLASS(ms); const SmpCachePropertiesList *node; DECLARE_BITMAP(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX); @@ -292,6 +329,44 @@ bool machine_parse_smp_cache(MachineState *ms, set_bit(node->value->cache, caches_bitmap); } + for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { + const SmpCacheProperties *props = &ms->smp_cache.props[i]; + + /* + * Reject non "default" topology level if the cache isn't + * supported by the machine. + */ + if (props->topology != CPU_TOPOLOGY_LEVEL_DEFAULT && + !mc->smp_props.cache_supported[props->cache]) { + error_setg(errp, + "%s cache topology not supported by this machine", + CacheLevelAndType_str(node->value->cache)); + return false; + } + + if (!machine_check_topo_support(ms, props->topology, errp)) { + return false; + } + } + + if (smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L1D, + CACHE_LEVEL_AND_TYPE_L2) || + smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L1I, + CACHE_LEVEL_AND_TYPE_L2)) { + error_setg(errp, + "Invalid smp cache topology. " + "L2 cache topology level shouldn't be lower than L1 cache"); + return false; + } + + if (smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L2, + CACHE_LEVEL_AND_TYPE_L3)) { + error_setg(errp, + "Invalid smp cache topology. " + "L3 cache topology level shouldn't be lower than L2 cache"); + return false; + } + return true; } diff --git a/include/hw/boards.h b/include/hw/boards.h index 0729066e353a..e4a1035e3fa1 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -151,6 +151,8 @@ typedef struct { * @books_supported - whether books are supported by the machine * @drawers_supported - whether drawers are supported by the machine * @modules_supported - whether modules are supported by the machine + * @cache_supported - whether cache (l1d, l1i, l2 and l3) configuration are + * supported by the machine */ typedef struct { bool prefer_sockets; @@ -160,6 +162,7 @@ typedef struct { bool books_supported; bool drawers_supported; bool modules_supported; + bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX]; } SMPCompatProps; /**