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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB53.mail.protection.outlook.com (10.167.241.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8114.16 via Frontend Transport; Mon, 28 Oct 2024 05:35:38 +0000 Received: from gomati.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Oct 2024 00:35:34 -0500 From: Nikunj A Dadhania To: , , , , CC: , , , , , , Subject: [PATCH v14 08/13] x86/cpu/amd: Do not print FW_BUG for Secure TSC Date: Mon, 28 Oct 2024 11:04:26 +0530 Message-ID: <20241028053431.3439593-9-nikunj@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241028053431.3439593-1-nikunj@amd.com> References: <20241028053431.3439593-1-nikunj@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB53:EE_|DM3PR12MB9286:EE_ X-MS-Office365-Filtering-Correlation-Id: d92c094a-c9ef-4313-bf40-08dcf7125a95 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: HkjypUuIHZeaiu0ouLUADoOH69fm5x+HDwVJkQmaf64g/2cceFuiC3x+fXLOh6AgCa5sFyYfXAGYHEjArA1vNMp15WdOasSru+FU0WZKapWYCWSivQIsXNQItBTNS2AF5v8qmNuoxhlqiOwyJaBbmG0IAEx+vsMgc990hzjUDM11xFpWdyQqyEyH74RIAmc5SIXzprNk4zmMHVyhCcvz3cCL1gF9YytLMN1mANBuL1kTTN7y0LSfd9B/j1Pa/UUXihuQOr1fHoQCaONxW0FS69gB0a7K+ORb4Cpn5kDEM35wpH6WEfuSmsEfriVoPpGzMaq7l2221GeYvuYWcoECdLM9HiAdJIamWkJuqmir/LSPG8kLOrO82amNS8cVfIH6QFrOlrSfPjM6FTCRM5s5neSWzchrzlRLlYMZ77iymLdoIsecQhyUrde9QvwWLqjICI205JjfpQyRA+Pc+WVfURANT7QNhjdzHMR+AWs9oXxmijRDXEsjnhzAy0mAd8odTiAjmQz+/Bj792T2z9cU9OyibtYkG1LGaXmHt83ENplgfU4TO8Z85jScz6FAXynB2frzCNmsV5arMS4oV2VWh021ZiK605pjA6EPy5YsKeU13Qysj26EGL6CFKURlWjAPWSSgvxM3cP3xNKIf8ev0N5g3Fy+4cTTUSAsh6JecOFFXC321r8UFlp7+5jTMdY3kS5/fE8ruKKsDL9wa6z9TVTan+V6VuVKPUhEEfAMTrjGC/ryHQ+yRSG02sviJDk/MhbGVw75ugDUTJ1zCoQ3L09jLBN7vgwpjq9We2p7a/NhD96jZL5gMAJAZ9v8/oqBZf7g72QfoNzUP7e+M13iqoLgzR6nhyqUdwxXu59mUNh15r82mFaWssPWoidOYTYYKmXIKl1i5cszGfFipPzzh2lHyg0PApkVCgHFxf5GNLpgJiGGHr8DsCQi7tZObmSYI/2dU3mQiGaaF+FTT58mQReSBEewH9eU3psIv3e0J7uetUMXDlGxRGjhMSNcLLFuBreZfS0ZTAn6fVT9gLBWGqlrlsGJed+xKa4fFQCYT/CCGD6HxEyYrW/BnNfHTbTYPUPfhL0aRcFwcxdz7JgtdHrJAoj9tVKsumwP7EMe1VEDbMSn4htkAFGJuNwQyKNK1QpHnJTmZCrtt5rGkGxnSAYaTj54goJrnf41aPe8iude4lQkVQGiB6H+BCgYnxNz54igMn7TUU/D9v1HnptwjwuDaAtl7HneQOI29SiBYBK50BbcdPOt62GTRWLyepAB9i6NTMGP+7M4/il0SekcSSvExMWHWle1IIKmljsfS/4C6B3+53eU3uUn6uD3nLulDUZ12GvxVmKbG0gRUC+tlPjUK2+yTFOzdWuePhT3n5wdIeS5EU+gmj0RjgHULVCmKBiRoIYM59OKO7+au9Ja9g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2024 05:35:38.0378 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d92c094a-c9ef-4313-bf40-08dcf7125a95 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB53.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9286 When Secure TSC is enabled and TscInvariant (bit 8) in CPUID_8000_0007_edx is set, the kernel complains with the below firmware bug: [Firmware Bug]: TSC doesn't count with P0 frequency! Secure TSC does not need to run at P0 frequency; the TSC frequency is set by the VMM as part of the SNP_LAUNCH_START command. Skip this check when Secure TSC is enabled Signed-off-by: Nikunj A Dadhania Tested-by: Peter Gonda Reviewed-by: Tom Lendacky --- arch/x86/kernel/cpu/amd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 015971adadfc..4769c10cba04 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -370,7 +370,8 @@ static void bsp_determine_snp(struct cpuinfo_x86 *c) static void bsp_init_amd(struct cpuinfo_x86 *c) { - if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { + if (cpu_has(c, X86_FEATURE_CONSTANT_TSC) && + !cc_platform_has(CC_ATTR_GUEST_SNP_SECURE_TSC)) { if (c->x86 > 0x10 || (c->x86 == 0x10 && c->x86_model >= 0x2)) {