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Mon, 11 Nov 2024 00:42:31 -0800 From: Yishai Hadas To: , , , CC: , , , , , , , , Subject: [PATCH V2 vfio 1/7] virtio_pci: Introduce device parts access commands Date: Mon, 11 Nov 2024 10:41:51 +0200 Message-ID: <20241111084157.88044-2-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20241111084157.88044-1-yishaih@nvidia.com> References: <20241111084157.88044-1-yishaih@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E8:EE_|SA3PR12MB7782:EE_ X-MS-Office365-Filtering-Correlation-Id: c43081b5-7f5f-40fa-9dff-08dd022cd3e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: cjVPSk2rrqrtDdK+3w2JwVY/lp0CUO+H/DyobGqAwk4MeejZJidoDCKMCFH9cvDQSSMidTgmiaHsSoG4ozguK0mXVDwwmMWRzY3BQMc/2qoWhI43B8lo/cy+z0ZVn13E2KcY3qwlIaWqVNNWgEzkzvLCR0wXqgi0wKI0nHot+CEH0VsIQo4sxk8GY9r572hpp1cpcmPV+smVstkv67+mKva3UbdPQoe5Ifba9R8OcLu05s9BPEvbNuG2cQt3MMUPdWiF24vzkbyDmNnD2XadFuwlr3ca6dBI0xWPoFZaSgK5AjV8ypMmcSCTpmfqQz8AHh6YQDfm0MZiVxF79kqxj9ibaP5ozgzuL/hsGtnB9qauX2teTrvptTiqHm3ptjs1CWmDSvVbDeONCZiWPyqX1y2b91RdaVn57d6QoZFzylBKWJJXV8ujB6GESaB25AgByOwAeaObyD+CHsk2jRL4QOQfEN1jRA01IJGc4e4IBa4mDf0l/Ziy/PIAQ2iXEhyyXEIsoE1mhQoDYEU+h3WMiLIPz/qGyCnCL4bE6wI2K6YraUx3YPoGdY8vB2SRrmD2xPeLkLFgpMMkxVTO74UCgPkv5sUefJK+vtoLeWuGDBUQtinu9Snqfl8hp8eXMwn61eLDBuCjW7QB8d24TwM5ZhQsOYJps4aKQwlYRMEXxsXlHqY9sVj+I83NPie82RFt2ezit09v3w5DgxVR04S7dGnWITL8Z7uEQHuz3aNRFVOyz64FH1m+zDpdHy53V08LbGIe8ehNOM2VrwkDEV4yTxdRcEITtxtBCKapQN7wUGB3kJ5J0GTwIVQxckPuA078GfmRxSKW750KZ6RRsP1aL9M4D1jsCQJ0MrIUXnVSzCkXiv+D1BorzGdrxv+GO5IbtKIH7/YL4dUa1hK5jzUqZbkwpVtKm0hkzcvK5yny7rpEfJffQPdOe7UdQR/XY2CseaBQFrJu80ueaEAe6GlLLLOKvtx9LXZbs2mbVmPTQ11a5lJTOnujp1lhJl6vJrOmhpV/sKR6UjusJL5WCvR4u3KXS8jIHhZDG3m9i2ZLNlMTbU140XP+VpMzxjWBIcbQrpK0AUpBDMBXYPD9/Qz9kDBJIXb+1UCtuEbRizYmtHBIiMkKtjpd3wA9B5rJMdpQF2nwI+q9A62eb4dWo7e+oyAD4F24uT5Qq03TaEdPJAwiw4t9vXYERzIKNCvsh1sF4VEACHleEe9NGAHYjfOInCWg5qOvr8XalGucAA77mdLAK28K9B+w5luJeaWmr+caDqKSbLtnCItydB8zaynECs39K1uFk293BS4/5Ga/mMIkdskoZJFJLnNMsj1204xePBfuxAI8Irapzd52FZqJdZ1lX5w+hzW1pEh7WA7lYyn/KuBroIdFrAznSOeh6iEhBazmgklFfZBKgDs/nnt4Ig== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2024 08:42:51.1969 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c43081b5-7f5f-40fa-9dff-08dd022cd3e8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7782 Introduce device parts access commands via the admin queue. These commands and their structure adhere to the Virtio 1.4 specification. Acked-by: Michael S. Tsirkin Signed-off-by: Yishai Hadas --- include/uapi/linux/virtio_pci.h | 131 ++++++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) diff --git a/include/uapi/linux/virtio_pci.h b/include/uapi/linux/virtio_pci.h index a8208492e822..1beb317df1b9 100644 --- a/include/uapi/linux/virtio_pci.h +++ b/include/uapi/linux/virtio_pci.h @@ -40,6 +40,7 @@ #define _LINUX_VIRTIO_PCI_H #include +#include #ifndef VIRTIO_PCI_NO_LEGACY @@ -240,6 +241,17 @@ struct virtio_pci_cfg_cap { #define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_READ 0x5 #define VIRTIO_ADMIN_CMD_LEGACY_NOTIFY_INFO 0x6 +/* Device parts access commands. */ +#define VIRTIO_ADMIN_CMD_CAP_ID_LIST_QUERY 0x7 +#define VIRTIO_ADMIN_CMD_DEVICE_CAP_GET 0x8 +#define VIRTIO_ADMIN_CMD_DRIVER_CAP_SET 0x9 +#define VIRTIO_ADMIN_CMD_RESOURCE_OBJ_CREATE 0xa +#define VIRTIO_ADMIN_CMD_RESOURCE_OBJ_DESTROY 0xd +#define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_GET 0xe +#define VIRTIO_ADMIN_CMD_DEV_PARTS_GET 0xf +#define VIRTIO_ADMIN_CMD_DEV_PARTS_SET 0x10 +#define VIRTIO_ADMIN_CMD_DEV_MODE_SET 0x11 + struct virtio_admin_cmd_hdr { __le16 opcode; /* @@ -286,4 +298,123 @@ struct virtio_admin_cmd_notify_info_result { struct virtio_admin_cmd_notify_info_data entries[VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO]; }; +#define VIRTIO_DEV_PARTS_CAP 0x0000 + +struct virtio_dev_parts_cap { + __u8 get_parts_resource_objects_limit; + __u8 set_parts_resource_objects_limit; +}; + +#define MAX_CAP_ID __KERNEL_DIV_ROUND_UP(VIRTIO_DEV_PARTS_CAP + 1, 64) + +struct virtio_admin_cmd_query_cap_id_result { + __le64 supported_caps[MAX_CAP_ID]; +}; + +struct virtio_admin_cmd_cap_get_data { + __le16 id; + __u8 reserved[6]; +}; + +struct virtio_admin_cmd_cap_set_data { + __le16 id; + __u8 reserved[6]; + __u8 cap_specific_data[]; +}; + +struct virtio_admin_cmd_resource_obj_cmd_hdr { + __le16 type; + __u8 reserved[2]; + __le32 id; /* Indicates unique resource object id per resource object type */ +}; + +struct virtio_admin_cmd_resource_obj_create_data { + struct virtio_admin_cmd_resource_obj_cmd_hdr hdr; + __le64 flags; + __u8 resource_obj_specific_data[]; +}; + +#define VIRTIO_RESOURCE_OBJ_DEV_PARTS 0 + +#define VIRTIO_RESOURCE_OBJ_DEV_PARTS_TYPE_GET 0 +#define VIRTIO_RESOURCE_OBJ_DEV_PARTS_TYPE_SET 1 + +struct virtio_resource_obj_dev_parts { + __u8 type; + __u8 reserved[7]; +}; + +#define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_TYPE_SIZE 0 +#define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_TYPE_COUNT 1 +#define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_TYPE_LIST 2 + +struct virtio_admin_cmd_dev_parts_metadata_data { + struct virtio_admin_cmd_resource_obj_cmd_hdr hdr; + __u8 type; + __u8 reserved[7]; +}; + +#define VIRTIO_DEV_PART_F_OPTIONAL 0 + +struct virtio_dev_part_hdr { + __le16 part_type; + __u8 flags; + __u8 reserved; + union { + struct { + __le32 offset; + __le32 reserved; + } pci_common_cfg; + struct { + __le16 index; + __u8 reserved[6]; + } vq_index; + } selector; + __le32 length; +}; + +struct virtio_dev_part { + struct virtio_dev_part_hdr hdr; + __u8 value[]; +}; + +struct virtio_admin_cmd_dev_parts_metadata_result { + union { + struct { + __le32 size; + __le32 reserved; + } parts_size; + struct { + __le32 count; + __le32 reserved; + } hdr_list_count; + struct { + __le32 count; + __le32 reserved; + struct virtio_dev_part_hdr hdrs[]; + } hdr_list; + }; +}; + +#define VIRTIO_ADMIN_CMD_DEV_PARTS_GET_TYPE_SELECTED 0 +#define VIRTIO_ADMIN_CMD_DEV_PARTS_GET_TYPE_ALL 1 + +struct virtio_admin_cmd_dev_parts_get_data { + struct virtio_admin_cmd_resource_obj_cmd_hdr hdr; + __u8 type; + __u8 reserved[7]; + struct virtio_dev_part_hdr hdr_list[]; +}; + +struct virtio_admin_cmd_dev_parts_set_data { + struct virtio_admin_cmd_resource_obj_cmd_hdr hdr; + struct virtio_dev_part parts[]; +}; + +#define VIRTIO_ADMIN_CMD_DEV_MODE_F_STOPPED 0 + +struct virtio_admin_cmd_dev_mode_set_data { + __u8 flags; +}; + #endif