diff mbox series

[kvm-unit-test,2/3] x86/pmu: Fixed PEBS basic record parsing issue

Message ID 20241118225207.16596-2-zide.chen@intel.com (mailing list archive)
State New
Headers show
Series [kvm-unit-test,1/3] nVMX: fixed-function performance counters could be not contiguous | expand

Commit Message

Zide Chen Nov. 18, 2024, 10:52 p.m. UTC 
If adaptive PEBS is supported, to parse the PEBS record_format[47:0],
SDM states that "This field indicates which data groups are included
in the record. The field is zero if none of the counters that triggered
the current PEBS record have their Adaptive_Record bit set. Otherwise
it contains the value of MSR_PEBS_DATA_CFG."

Without this fix, if neither IA32_PERFEVTSELx.Adaptive_Record[34] nor
IA32_FIXED_CTR_CTRL.FCx_Adaptive_Record is set on adaptive PEBS capable
systems, test will fail.

Fixes: 2cb2af7f53d ("x86/pmu: Test adaptive PEBS without any adaptive counters")
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
 x86/pmu_pebs.c | 2 ++
 1 file changed, 2 insertions(+)
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Patch

diff --git a/x86/pmu_pebs.c b/x86/pmu_pebs.c
index 77875c4fee35..6b4a5ed3b91e 100644
--- a/x86/pmu_pebs.c
+++ b/x86/pmu_pebs.c
@@ -297,6 +297,8 @@  static void check_pebs_records(u64 bitmask, u64 pebs_data_cfg, bool use_adaptive
 		pebs_idx_match = pebs_rec->applicable_counters & bitmask;
 		pebs_size_match = pebs_record_size == get_pebs_record_size(pebs_data_cfg, use_adaptive);
 		data_cfg_match = (pebs_rec->format_size & GENMASK_ULL(47, 0)) == pebs_data_cfg;
+		data_cfg_match = (pebs_rec->format_size & GENMASK_ULL(47, 0)) ==
+				 (use_adaptive ? pebs_data_cfg : 0);
 		expected = pebs_idx_match && pebs_size_match && data_cfg_match;
 		report(expected,
 		       "PEBS record (written seq %d) is verified (including size, counters and cfg).", count);