From patchwork Mon Dec 2 17:21:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13891098 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B965D1D9A6E; Mon, 2 Dec 2024 17:22:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733160138; cv=none; b=iFE4t0LyOAqqCFZfuQFY/ic4OxrpNusBPVLuk7eHfxH6qgJuh7zehEEr/Jt2qIwZq9Sdyhtn7mn6NYFmWjfwANOzh7kXH/UFQhF6OqgNqdPEUh4Bc+2qNPgI6IIwnBty/LL6qnzMdTlXZ9Gcae2hqe/PiTwMjv+zK1l83yZHLkQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733160138; c=relaxed/simple; bh=IIrtI7EOvJLa54PAnEtwLydgd3SRuxhX3ocldVjdaE4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Fk5pT+tuSq+4pMQVkDiFsBT5Y6NTmR6O1YrVN5+97GfLQdh6hNcf2hS+WvCsZSGAZSpkueBYR5p2eMC867tAOCxdQAVgJ2yzo9pAdgSHLCR4NDx2n82MVF6dNfd251pxhP/lnfcl49BOlTLnVwYNtcM7bE4uZJbPH4QyIXTZ0Bc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=c2iBSwDI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="c2iBSwDI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 41C3AC4CEDD; Mon, 2 Dec 2024 17:22:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733160138; bh=IIrtI7EOvJLa54PAnEtwLydgd3SRuxhX3ocldVjdaE4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c2iBSwDIdRq02VTsVhiBzvFgP8aaWXi5YstePFY2Zdi67SIAJbmAv0RE8SRFnbSls homdfVhG0zJpfAqwtDIxmCuXNrP2W3raEtpqSDcuEDjVcIyQY8/GpaEPJYDf1hS80O CT6qTAfoInxEDmFgOGcWqUHafYWJSH2kko59GIqHSTjuh1/IeE5NUmMQSZGPLg5ey0 CprPFAiDJvUg+pq7X7rc32XM96EwZjlnKPrqQjvVysv8mUk+OImgO+gbB3kbxn7y6P IQCHFyRkgfg0gzd7tN+K+CJsZ7dBLOMpvVb04GhY3sT7ZLJJL1keuvc3qwKdrhK+8s C3ravH5jK4PEQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tIA7k-00HQcf-BN; Mon, 02 Dec 2024 17:22:16 +0000 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Bjorn Andersson , Christoffer Dall , Chase Conklin , Ganapatrao Kulkarni Subject: [PATCH 03/11] KVM: arm64: nv: Publish emulated timer interrupt state in the in-memory state Date: Mon, 2 Dec 2024 17:21:26 +0000 Message-Id: <20241202172134.384923-4-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241202172134.384923-1-maz@kernel.org> References: <20241202172134.384923-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, andersson@kernel.org, christoffer.dall@arm.com, chase.conklin@arm.com, gankulkarni@os.amperecomputing.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false With FEAT_NV2, the EL0 timer state is entirely stored in memory, meaning that the hypervisor can only provide a very poor emulation. The only thing we can really do is to publish the interrupt state in the guest view of CNT{P,V}_CTL_EL0, and defer everything else to the next exit. Only FEAT_ECV will allow us to fix it, at the cost of extra trapping. Suggested-by: Chase Conklin Suggested-by: Ganapatrao Kulkarni Signed-off-by: Marc Zyngier --- arch/arm64/kvm/arch_timer.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index 81afafd62059f..231040090697e 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -446,6 +446,25 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level, { int ret; + /* + * Paper over NV2 brokenness by publishing the interrupt status + * bit. This still results in a poor quality of emulation (guest + * writes will have no effect until the next exit). + * + * But hey, it's fast, right? + */ + if (is_hyp_ctxt(vcpu) && + (timer_ctx == vcpu_vtimer(vcpu) || timer_ctx == vcpu_ptimer(vcpu))) { + u32 ctl = timer_get_ctl(timer_ctx); + + if (new_level) + ctl |= ARCH_TIMER_CTRL_IT_STAT; + else + ctl &= ~ARCH_TIMER_CTRL_IT_STAT; + + timer_set_ctl(timer_ctx, ctl); + } + timer_ctx->irq.level = new_level; trace_kvm_timer_update_irq(vcpu->vcpu_id, timer_irq(timer_ctx), timer_ctx->irq.level);