| Message ID | 20250207032634.2333300-4-maobibo@loongson.cn (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | LoongArch: KVM: Some tiny code cleanup | expand |
Hi, Bibo, On Fri, Feb 7, 2025 at 11:26 AM Bibo Mao <maobibo@loongson.cn> wrote: > > PRMD and ERA register is only meaningful on the beginning stage > of exception entry, and it can be overwritten for nested irq or > exception. The code doesn't touch ERA, so ERA in the commit message is a typo? Huacai > > When CPU runs in VM mode, interrupt need be enabled on host. And the > mode for host had better be kernel mode rather than random. > > Signed-off-by: Bibo Mao <maobibo@loongson.cn> > --- > arch/loongarch/kvm/switch.S | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/loongarch/kvm/switch.S b/arch/loongarch/kvm/switch.S > index 0c292f818492..1be185e94807 100644 > --- a/arch/loongarch/kvm/switch.S > +++ b/arch/loongarch/kvm/switch.S > @@ -85,7 +85,7 @@ > * Guest CRMD comes from separate GCSR_CRMD register > */ > ori t0, zero, CSR_PRMD_PIE > - csrxchg t0, t0, LOONGARCH_CSR_PRMD > + csrwr t0, LOONGARCH_CSR_PRMD > > /* Set PVM bit to setup ertn to guest context */ > ori t0, zero, CSR_GSTAT_PVM > -- > 2.39.3 >
On 2025/2/9 下午5:47, Huacai Chen wrote: > Hi, Bibo, > > On Fri, Feb 7, 2025 at 11:26 AM Bibo Mao <maobibo@loongson.cn> wrote: >> >> PRMD and ERA register is only meaningful on the beginning stage >> of exception entry, and it can be overwritten for nested irq or >> exception. > The code doesn't touch ERA, so ERA in the commit message is a typo? oh, ERA is redundant here. Will remove it in next version. Regards Bibo Mao > > Huacai >> >> When CPU runs in VM mode, interrupt need be enabled on host. And the >> mode for host had better be kernel mode rather than random. >> >> Signed-off-by: Bibo Mao <maobibo@loongson.cn> >> --- >> arch/loongarch/kvm/switch.S | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/loongarch/kvm/switch.S b/arch/loongarch/kvm/switch.S >> index 0c292f818492..1be185e94807 100644 >> --- a/arch/loongarch/kvm/switch.S >> +++ b/arch/loongarch/kvm/switch.S >> @@ -85,7 +85,7 @@ >> * Guest CRMD comes from separate GCSR_CRMD register >> */ >> ori t0, zero, CSR_PRMD_PIE >> - csrxchg t0, t0, LOONGARCH_CSR_PRMD >> + csrwr t0, LOONGARCH_CSR_PRMD >> >> /* Set PVM bit to setup ertn to guest context */ >> ori t0, zero, CSR_GSTAT_PVM >> -- >> 2.39.3 >>
diff --git a/arch/loongarch/kvm/switch.S b/arch/loongarch/kvm/switch.S index 0c292f818492..1be185e94807 100644 --- a/arch/loongarch/kvm/switch.S +++ b/arch/loongarch/kvm/switch.S @@ -85,7 +85,7 @@ * Guest CRMD comes from separate GCSR_CRMD register */ ori t0, zero, CSR_PRMD_PIE - csrxchg t0, t0, LOONGARCH_CSR_PRMD + csrwr t0, LOONGARCH_CSR_PRMD /* Set PVM bit to setup ertn to guest context */ ori t0, zero, CSR_GSTAT_PVM
PRMD and ERA register is only meaningful on the beginning stage of exception entry, and it can be overwritten for nested irq or exception. When CPU runs in VM mode, interrupt need be enabled on host. And the mode for host had better be kernel mode rather than random. Signed-off-by: Bibo Mao <maobibo@loongson.cn> --- arch/loongarch/kvm/switch.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)