| Message ID | 20250220141354.2565567-2-joey.gouly@arm.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: support EL2 | expand |
On Thu, 20 Feb 2025 14:13:48 +0000, Joey Gouly <joey.gouly@arm.com> wrote: > > EL2 is not currently supported, drop to EL1 to conitnue booting. > > Signed-off-by: Joey Gouly <joey.gouly@arm.com> > --- > arm/cstart64.S | 27 +++++++++++++++++++++++++-- > 1 file changed, 25 insertions(+), 2 deletions(-) > > diff --git a/arm/cstart64.S b/arm/cstart64.S > index b480a552..3a305ad0 100644 > --- a/arm/cstart64.S > +++ b/arm/cstart64.S > @@ -57,14 +57,25 @@ start: > add x6, x6, :lo12:reloc_end > 1: > cmp x5, x6 > - b.hs 1f > + b.hs reloc_done > ldr x7, [x5] // r_offset > ldr x8, [x5, #16] // r_addend > add x8, x8, x4 // val = base + r_addend > str x8, [x4, x7] // base[r_offset] = val > add x5, x5, #24 > b 1b > - > +reloc_done: > + mrs x4, CurrentEL > + cmp x4, CurrentEL_EL2 > + b.ne 1f > +drop_to_el1: > + mov x4, 4 It'd be nice to have a symbolic constant denoting EL1t. > + msr spsr_el2, x4 > + adrp x4, 1f > + add x4, x4, :lo12:1f > + msr elr_el2, x4 > + isb You can drop this ISB, as the following ERET has the same context synchronisation properties. > + eret > 1: > /* zero BSS */ > adrp x4, bss > @@ -186,6 +197,18 @@ get_mmu_off: > > .globl secondary_entry > secondary_entry: > + mrs x0, CurrentEL > + cmp x0, CurrentEL_EL2 > + b.ne 1f > +drop_to_el1_secondary: > + mov x0, 4 > + msr spsr_el2, x0 > + adrp x0, 1f > + add x0, x0, :lo12:1f > + msr elr_el2, x0 > + isb > + eret Maybe move this into a macro and use it in the two instances of EL2->EL1 drop. > +1: > /* enable FP/ASIMD and SVE */ > mov x0, #(3 << 20) > orr x0, x0, #(3 << 16) Thanks, M.
diff --git a/arm/cstart64.S b/arm/cstart64.S index b480a552..3a305ad0 100644 --- a/arm/cstart64.S +++ b/arm/cstart64.S @@ -57,14 +57,25 @@ start: add x6, x6, :lo12:reloc_end 1: cmp x5, x6 - b.hs 1f + b.hs reloc_done ldr x7, [x5] // r_offset ldr x8, [x5, #16] // r_addend add x8, x8, x4 // val = base + r_addend str x8, [x4, x7] // base[r_offset] = val add x5, x5, #24 b 1b - +reloc_done: + mrs x4, CurrentEL + cmp x4, CurrentEL_EL2 + b.ne 1f +drop_to_el1: + mov x4, 4 + msr spsr_el2, x4 + adrp x4, 1f + add x4, x4, :lo12:1f + msr elr_el2, x4 + isb + eret 1: /* zero BSS */ adrp x4, bss @@ -186,6 +197,18 @@ get_mmu_off: .globl secondary_entry secondary_entry: + mrs x0, CurrentEL + cmp x0, CurrentEL_EL2 + b.ne 1f +drop_to_el1_secondary: + mov x0, 4 + msr spsr_el2, x0 + adrp x0, 1f + add x0, x0, :lo12:1f + msr elr_el2, x0 + isb + eret +1: /* enable FP/ASIMD and SVE */ mov x0, #(3 << 20) orr x0, x0, #(3 << 16)
EL2 is not currently supported, drop to EL1 to conitnue booting. Signed-off-by: Joey Gouly <joey.gouly@arm.com> --- arm/cstart64.S | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-)