From patchwork Mon Mar 10 12:24:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 14009834 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 604FD22A4D3; Mon, 10 Mar 2025 12:25:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741609515; cv=none; b=kUe0Pm9YdDdJkny2GS6rg1rilu3hGwI8wtNHZODj7YqbYEfqiTMMknhsFize26zcZvoZYFAuRSbStuqSQc0kK3Ull0gLbJzCMMO4Z5Fsn7tKg+2jpjfP1bGpvgQ5xUv5xeAvbOha7wbIaV8XWKq/R/b3oR6801grY621fCEeI8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741609515; c=relaxed/simple; bh=UE+/Jn0v1kpPCg3Ww5aujoS3ZhYVP55Hgh9LzEWu0kA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aNMdkHH6h9heoqyRYLuNK2+XJs3d8BYf/TcdRTIFCKhpW3PHzeOc4gGg2JelGBRTT0vfe2Z4t2fcRPlBLiZelbmRnN8FyugScLxwSl/VROhaGGsPAnZuXew8clRWEE0mLWEw+1LC+pY+4f2hCPFfz0H6gEA6kRGGAlUaL4bcr3o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Dei6BMT1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Dei6BMT1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 37D6BC4CEF5; Mon, 10 Mar 2025 12:25:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1741609515; bh=UE+/Jn0v1kpPCg3Ww5aujoS3ZhYVP55Hgh9LzEWu0kA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Dei6BMT1QS/oBTMv64uBPNvvP6j+MFw/RKDT3WBxAg68u8OWNBW26p/MEa5HYXHPQ WF9kd/9hNWajRAo8C7daPgfeQj5iI3sRljITL1Gtx5I7eyBKTieCMxaF5AFQbwpv4w Z+Pc5g7yQfKdW+Yq26YcOlJ7JiJWY9kldy40pNVtPFOeffUMyzN8nGE+Ni2p228XsL uO5/FsID/qrR+MQd+8CAUsZK5yc6TLRVgJxiidjUqNf7xV4wRH5erxhv55bO3cL6KB oVWrhtdI5xpwrMYSLB8P2cVQk+oA8TmHBIVImeYsA62p/eFknmNdNUnJCku8kpDhQv kU3gjmxUqTeAw== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1trcC1-00CAea-C2; Mon, 10 Mar 2025 12:25:13 +0000 From: Marc Zyngier To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Mark Rutland , Fuad Tabba Subject: [PATCH v2 13/23] KVM: arm64: Propagate FGT masks to the nVHE hypervisor Date: Mon, 10 Mar 2025 12:24:55 +0000 Message-Id: <20250310122505.2857610-14-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250310122505.2857610-1-maz@kernel.org> References: <20250310122505.2857610-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, mark.rutland@arm.com, tabba@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false The nVHE hypervisor needs to have access to its own view of the FGT masks, which unfortunately results in a bit of data duplication. Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/kvm_host.h | 7 +++++++ arch/arm64/kvm/arm.c | 8 ++++++++ arch/arm64/kvm/hyp/nvhe/switch.c | 7 +++++++ 3 files changed, 22 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 657fb8243ea63..78ae52e4f48b0 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -583,6 +583,13 @@ extern struct fgt_masks hdfgrtr_masks; extern struct fgt_masks hdfgwtr_masks; extern struct fgt_masks hafgrtr_masks; +extern struct fgt_masks kvm_nvhe_sym(hfgrtr_masks); +extern struct fgt_masks kvm_nvhe_sym(hfgwtr_masks); +extern struct fgt_masks kvm_nvhe_sym(hfgitr_masks); +extern struct fgt_masks kvm_nvhe_sym(hdfgrtr_masks); +extern struct fgt_masks kvm_nvhe_sym(hdfgwtr_masks); +extern struct fgt_masks kvm_nvhe_sym(hafgrtr_masks); + struct kvm_cpu_context { struct user_pt_regs regs; /* sp = sp_el0 */ diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index b8e55a441282f..b5ee4669fe7cb 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -2414,6 +2414,14 @@ static void kvm_hyp_init_symbols(void) kvm_nvhe_sym(__icache_flags) = __icache_flags; kvm_nvhe_sym(kvm_arm_vmid_bits) = kvm_arm_vmid_bits; + /* Propagate the FGT state to the the nVHE side */ + kvm_nvhe_sym(hfgrtr_masks) = hfgrtr_masks; + kvm_nvhe_sym(hfgwtr_masks) = hfgwtr_masks; + kvm_nvhe_sym(hfgitr_masks) = hfgitr_masks; + kvm_nvhe_sym(hdfgrtr_masks) = hdfgrtr_masks; + kvm_nvhe_sym(hdfgwtr_masks) = hdfgwtr_masks; + kvm_nvhe_sym(hafgrtr_masks) = hafgrtr_masks; + /* * Flush entire BSS since part of its data containing init symbols is read * while the MMU is off. diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c index 7d2ba6ef02618..ae55d6d87e3d2 100644 --- a/arch/arm64/kvm/hyp/nvhe/switch.c +++ b/arch/arm64/kvm/hyp/nvhe/switch.c @@ -33,6 +33,13 @@ DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); +struct fgt_masks hfgrtr_masks; +struct fgt_masks hfgwtr_masks; +struct fgt_masks hfgitr_masks; +struct fgt_masks hdfgrtr_masks; +struct fgt_masks hdfgwtr_masks; +struct fgt_masks hafgrtr_masks; + extern void kvm_nvhe_prepare_backtrace(unsigned long fp, unsigned long pc); static void __activate_cptr_traps(struct kvm_vcpu *vcpu)