From patchwork Sat Jul 1 00:26:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Feiner X-Patchwork-Id: 9820651 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5D1E960375 for ; Sat, 1 Jul 2017 00:26:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5178626E1A for ; Sat, 1 Jul 2017 00:26:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4653427CAF; Sat, 1 Jul 2017 00:26:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C907B26E1A for ; Sat, 1 Jul 2017 00:26:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752042AbdGAA0k (ORCPT ); Fri, 30 Jun 2017 20:26:40 -0400 Received: from mail-pg0-f52.google.com ([74.125.83.52]:33074 "EHLO mail-pg0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751817AbdGAA0i (ORCPT ); Fri, 30 Jun 2017 20:26:38 -0400 Received: by mail-pg0-f52.google.com with SMTP id f127so70366571pgc.0 for ; Fri, 30 Jun 2017 17:26:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=vY0mRpNzbzQBFo31DbY4nUCpybXMsY+GgszvWeaF+n4=; b=sMhttyjTK+g/396ntu6lMmeLnOilSNGhcK6IH95N/d/sJooowvfSo2HAnqN7Ylf6zG TIerDwEgKqZ2kuxejKqXZ6eo6HwvS1/STbge3hnAC7nmLn4638BbbLM3Mg09gvw6Px0d iFA7WeG/68MqwjFIvkEv1dRrnrP4njHX0m/Vn4be11+syabz6o3Ovwf3bGotyd6u/Uoe ewtvZs7ajpftYTzaBRpArlwfVEIKGnbv5p+GJC8XVsdPuhHwxiKHKxmJ8tB7VG68q9t+ wjNNrwa3jF9kMmW5ph2KbpNoEeyQUfIUCxUhovzDepAfIeBRq4N3mMWXkCF1oAaLLPZV iStA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=vY0mRpNzbzQBFo31DbY4nUCpybXMsY+GgszvWeaF+n4=; b=J0mDr1sLX2aNsD7fS/eYWA0Y+bNs93gTZcauWj7hBwcUty0zpnMEbRDF24bHPNCjVc G/EmVRLrX7Z9rjKUol7nGJKyBtoI8yMT0dFLoiS21pTEy3m3spPGn/g7nq8dXd9NnnZe 9fCP5/ARtW7944DrXtx3InvtZ4NO9ZMiIPvm5tacf+btDl+0/qTPC74V7UiMX1n6d0C7 kZ8tMFFdeWAvXFO4KpCzhvyOrjbxqoKVL8lES8rSz18RnWEdxWwOr8LYmjdji1pSLWhU Ceil6SxG71H2mP3MQzIW4h3sRUEr8MtbtWFsanhlwVadqHJm3SwJ3q39VAp/dnpwqKL1 RPXQ== X-Gm-Message-State: AKS2vOyk718556TO/hwhhgThzjius282x2mhMNZYBtqKYoEoOraQ6iu5 pmZ+kK8MU4Po86ELbwWR0Q== X-Received: by 10.84.129.35 with SMTP id 32mr27332453plb.165.1498868796961; Fri, 30 Jun 2017 17:26:36 -0700 (PDT) Received: from localhost ([2620:0:1009:3:4123:6f60:64cb:d807]) by smtp.gmail.com with ESMTPSA id c62sm19226555pfb.93.2017.06.30.17.26.36 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 30 Jun 2017 17:26:36 -0700 (PDT) From: Peter Feiner To: kvm@vger.kernel.org Cc: Paolo Bonzini , David Matlack , Peter Feiner Subject: [PATCH 2/4] x86: kvm: mmu: make spte mmio mask more explicit Date: Fri, 30 Jun 2017 17:26:30 -0700 Message-Id: <204674b7e67bd3eecead0ea9941b71e83c1cb7c8.1498868316.git.pfeiner@google.com> X-Mailer: git-send-email 2.13.2.725.g09c95d1e9-goog In-Reply-To: References: In-Reply-To: References: Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Specify both a mask (i.e., bits to consider) and a value (i.e., pattern of bits that indicates a special PTE) for mmio SPTEs. On Intel, this lets us pack even more information into the (SPTE_SPECIAL_MASK | EPT_VMX_RWX_MASK) mask we use for access tracking liberating all (SPTE_SPECIAL_MASK | (non-misconfigured-RWX)) values. Signed-off-by: Peter Feiner --- arch/x86/kvm/mmu.c | 9 ++++++--- arch/x86/kvm/mmu.h | 2 +- arch/x86/kvm/vmx.c | 3 ++- arch/x86/kvm/x86.c | 2 +- 4 files changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index dfd4cd67e5a6..10b3cfc7b411 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -183,6 +183,7 @@ static u64 __read_mostly shadow_user_mask; static u64 __read_mostly shadow_accessed_mask; static u64 __read_mostly shadow_dirty_mask; static u64 __read_mostly shadow_mmio_mask; +static u64 __read_mostly shadow_mmio_value; static u64 __read_mostly shadow_present_mask; /* @@ -207,8 +208,10 @@ static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIF static void mmu_spte_set(u64 *sptep, u64 spte); static void mmu_free_roots(struct kvm_vcpu *vcpu); -void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask) +void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value) { + BUG_ON((mmio_mask & mmio_value) != mmio_value); + shadow_mmio_value = mmio_value | SPTE_SPECIAL_MASK; shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK; } EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); @@ -270,7 +273,7 @@ static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, u64 mask = generation_mmio_spte_mask(gen); access &= ACC_WRITE_MASK | ACC_USER_MASK; - mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT; + mask |= shadow_mmio_value | access | gfn << PAGE_SHIFT; trace_mark_mmio_spte(sptep, gfn, access, gen); mmu_spte_set(sptep, mask); @@ -278,7 +281,7 @@ static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, static bool is_mmio_spte(u64 spte) { - return (spte & shadow_mmio_mask) == shadow_mmio_mask; + return (spte & shadow_mmio_mask) == shadow_mmio_value; } static gfn_t get_mmio_spte_gfn(u64 spte) diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h index 27975807cc64..41d362e95681 100644 --- a/arch/x86/kvm/mmu.h +++ b/arch/x86/kvm/mmu.h @@ -51,7 +51,7 @@ static inline u64 rsvd_bits(int s, int e) return ((1ULL << (e - s + 1)) - 1) << s; } -void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask); +void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value); void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context); diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index c6dec552b28f..e59b01a1d431 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -5163,7 +5163,8 @@ static void ept_set_mmio_spte_mask(void) * EPT Misconfigurations can be generated if the value of bits 2:0 * of an EPT paging-structure entry is 110b (write/execute). */ - kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE); + kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, + VMX_EPT_MISCONFIG_WX_VALUE); } #define VMX_XSS_EXIT_BITMAP 0 diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index a2cd0997343c..ac6eb99b99b5 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -6009,7 +6009,7 @@ static void kvm_set_mmio_spte_mask(void) mask &= ~1ull; #endif - kvm_mmu_set_mmio_spte_mask(mask); + kvm_mmu_set_mmio_spte_mask(mask, mask); } #ifdef CONFIG_X86_64