From patchwork Mon Feb 26 08:26:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 13571508 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 232416E5E4; Mon, 26 Feb 2024 08:28:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708936121; cv=none; b=MV9rvXCTES6Z4/U8fzT313F7G6mp61Na6i0YUJtrESG3hFG2SjuUj/iW++tkgnaJDngHnOecrRLGlAsa8P1LqjGIfLn4+VQLF8gvinHDcPm3A9g/hDuam6dPbsNBdJ0+EVDLxP4L8vSrinSvcp3HO75G5H2pHWG7VHXjXjeUXOQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708936121; c=relaxed/simple; bh=UdHZZK+7HP69uy+KRU1ryfGK1QyA5zHgajtOtOag5f4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aNBd5NIOSnDSIhQCrOZVopaU4C/IIa6DBj4y/NLr/O5jhzzErxYPYCuX2TtLjAFx44pJWUuRS3/SqpDZMgLdtBpo8nHzuneJJaHszCTfm89okaSJBuwmOiEe05NHGAcHgy5LU4dRYTqhupjyB8cz9xCs+xpRU2FqmArI1+KfY2Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=KMGCGt8o; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="KMGCGt8o" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708936119; x=1740472119; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UdHZZK+7HP69uy+KRU1ryfGK1QyA5zHgajtOtOag5f4=; b=KMGCGt8op5ApiszUjlILznFk/fwt0U1eFg2Uf1TXr5+Pq796q27/afre +1iRU6ZTLComkNe3tb2KgMkWIhvS2mAw3zP47MTiMR6a0raaSLMSVZxsG j/VYMm4kri0/8qUaMvNst2z2esHTTIwUmlCLChg2nbwPbhcN80DP7dUKy 0mQ2hlaqaxNVX2xnsP1iii497hIHrcYFqKbK8iSNdzhZ0cDXr1XUWPatj Mb5+IZp3uI5qEzq890B+EBWn6zD2Mlt9q0X9F+f49R41AmoqleiQf1AYk zjfxpTieiBA9sRVzPc7sjiQOaVCz3PrYOZauFAw28/rwd5uKTiOJVZQnG Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10995"; a="3069507" X-IronPort-AV: E=Sophos;i="6.06,185,1705392000"; d="scan'208";a="3069507" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2024 00:28:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,185,1705392000"; d="scan'208";a="11272534" Received: from ls.sc.intel.com (HELO localhost) ([172.25.112.31]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2024 00:28:37 -0800 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , Kai Huang , chen.bo@intel.com, hang.yuan@intel.com, tina.zhang@intel.com Subject: [PATCH v19 080/130] KVM: TDX: restore host xsave state when exit from the guest TD Date: Mon, 26 Feb 2024 00:26:22 -0800 Message-Id: <2894ed10014279f4b8caab582e3b7e7061b5dad3.1708933498.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Isaku Yamahata On exiting from the guest TD, xsave state is clobbered. Restore xsave state on TD exit. Signed-off-by: Isaku Yamahata --- v19: - Add EXPORT_SYMBOL_GPL(host_xcr0) v15 -> v16: - Added CET flag mask Signed-off-by: Isaku Yamahata --- arch/x86/kvm/vmx/tdx.c | 19 +++++++++++++++++++ arch/x86/kvm/x86.c | 1 + 2 files changed, 20 insertions(+) diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index 9616b1aab6ce..199226c6cf55 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -2,6 +2,7 @@ #include #include +#include #include #include "capabilities.h" @@ -534,6 +535,23 @@ void tdx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) */ } +static void tdx_restore_host_xsave_state(struct kvm_vcpu *vcpu) +{ + struct kvm_tdx *kvm_tdx = to_kvm_tdx(vcpu->kvm); + + if (static_cpu_has(X86_FEATURE_XSAVE) && + host_xcr0 != (kvm_tdx->xfam & kvm_caps.supported_xcr0)) + xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); + if (static_cpu_has(X86_FEATURE_XSAVES) && + /* PT can be exposed to TD guest regardless of KVM's XSS support */ + host_xss != (kvm_tdx->xfam & + (kvm_caps.supported_xss | XFEATURE_MASK_PT | TDX_TD_XFAM_CET))) + wrmsrl(MSR_IA32_XSS, host_xss); + if (static_cpu_has(X86_FEATURE_PKU) && + (kvm_tdx->xfam & XFEATURE_MASK_PKRU)) + write_pkru(vcpu->arch.host_pkru); +} + static noinstr void tdx_vcpu_enter_exit(struct vcpu_tdx *tdx) { struct tdx_module_args args; @@ -609,6 +627,7 @@ fastpath_t tdx_vcpu_run(struct kvm_vcpu *vcpu) tdx_vcpu_enter_exit(tdx); + tdx_restore_host_xsave_state(vcpu); tdx->host_state_need_restore = true; vcpu->arch.regs_avail &= ~VMX_REGS_LAZY_LOAD_SET; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 23ece956c816..b361d948140f 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -315,6 +315,7 @@ const struct kvm_stats_header kvm_vcpu_stats_header = { }; u64 __read_mostly host_xcr0; +EXPORT_SYMBOL_GPL(host_xcr0); static struct kmem_cache *x86_emulator_cache;