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Wysocki" , Shameerali Kolothum Thodi , Mostafa Saleh Subject: [PATCH v3 4/9] iommu/arm-smmu-v3: Report IOMMU_CAP_ENFORCE_CACHE_COHERENCY for CANWBS Date: Wed, 9 Oct 2024 13:23:10 -0300 Message-ID: <4-v3-e2e16cd7467f+2a6a1-smmuv3_nesting_jgg@nvidia.com> In-Reply-To: <0-v3-e2e16cd7467f+2a6a1-smmuv3_nesting_jgg@nvidia.com> References: X-ClientProxiedBy: BL1PR13CA0025.namprd13.prod.outlook.com (2603:10b6:208:256::30) To CH3PR12MB8659.namprd12.prod.outlook.com (2603:10b6:610:17c::13) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PR12MB8659:EE_|SJ1PR12MB6073:EE_ X-MS-Office365-Filtering-Correlation-Id: fdaad5cd-7566-4a9b-e640-08dce87eae34 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024|921020; X-Microsoft-Antispam-Message-Info: 8l7TPVPIUxftarXeh6xoov6stLFcFUajRZ0AQWDehlA6lXrgcjTufwTLqjzyJ6+vTAvzAnqEp2zoeAWzSwBUJlYk/xueKOThrwFrzwEF3zWZRGg1+0yHuCcf4uYafoGk0aMRA7M7kXpV1rcuidZ1o/8vnJKneDNg2EoIql3r74f1/J0i5h2LstUAHJtBLk40dINnIjAoZcYOKrFb3NaiEJgB6weX/LM2z9nfuXTqyeTY0PmY1L7q4ZKi7u3fjmnqPaj4FHL6ylkB8knc6dtJiOFouD2fncckchmPsIYT5jAfRha5TI9CzwKd6GXGlrQ6UUVRZ4+u8pdyiMAhSqB8CBzkfN5XkzYjr+vUChWfPG6kkSAObZrKANrybdC+qv6rvBR+YbM8wNwd3q4ErKivW2GTemZxOJN7sev72QJZKD27y2vpCZ9lUkcQc3ayUAZyDt2wLOBuGEgzOT9ZLk2VUV0eY/7da00j+Rl/YSxToBrYAwdex8ToiHAjjv9fb8/zd2RcT+bPvas5IWz8YnB/NFsbykkDjI+TgwDeEt6pVZgCFWHGJyQq4u3tJ7fpCOYNQKsJrW1k1OQ599u3fTgQW0XbrQ5mJiLwR7aGTxmIZU0Xs5jhZylv1c+KFV9+7vgb15l6cw7/R+L9s/yeVoGRXIcdN0R3k8r02u4HKVThCOwqxzNXDkcUs9RowfVD0+NINIAX9esvxKNbTsXIPd+7DKoPMHhIwerLhgsBnSJWB8bcJkbZxSWRVqHLcL9IcPvP/mdxHnBQqOKpzQoCbi9L1sljX5My+bM8Awdex83X+7ersGi/nfw7267wHQ3U/AcaJCRJulmV8fmbAu77azMrpDo1gOPnyf9KDtUJEc2+L9jaoQcSOGXjk3WXHebizXXf3C6avigoUbg2/A9W8kW+qoU9lwGMv4jGHzA4HFx/WlSTWFMuvLSX4Am43NaDryzKIV4mA0mi9phA678pAeFoG6nydDZR/NUiB49PY1ubxBvB5ifiZkYaDKR8xappsjSuz8OVkdKSvXJJJKy+6zboesR/35WlCOlk3XL8dsxvJAW4k4O/M8VIp+WsPNmm02jPeuk47Mhaet4va2fjJsKcc7PjH79pQQHFleT1J2/YP3jnzyC4PTrTf3efqe3idUH01vkbDBNGQGE4X9UH2wzvz6ZT00tYWXul9qJERTXGuxXYFdzdSqNBpqmf+CxZXyoUd/X5OxWHQYilPe3AJBquuBugHJKy8FDqyyT0ZSnNgFxhDcWNg/fYhEYhQMY4kzcElYbkf0+FTmtHUj9hmIzF38yXgINqhHkUFRp5ovRGYpLKPU9LcW/qCC9/RyeucMhr X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH3PR12MB8659.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ipMbwgG8999eMqS3NGhX+qqv1Dyqc41YuoLPJdhYlwQe7YkpcKRoxDnD9qyDu32nhr9PfRsk0zyER77xTXurjj7hS3NMsHdDFulrNW/QP6bxLNK5gRlCZw0OGfoJrdiuzzHZEEr/wRtofgBuivnX7bQuSx2ctCIno96a0HWoEk4fss7Ch2dVFIWPR8Tmg5U41uXFT4TaPUZ2FhwqxaPRg/p7MclbsoRjvajx3zYjr7DnNjp6ZPThQ5KgAKdKE85utyqPOcVZBqjK+SynLH+J8Mrg8smDQRCHgAd9e1cDE/F1k4cgG/sbGmqOAu9e7EMRAFQrHefDiqesG9Cg/zmk2VInJ1ff0eQwUcBTwXiC+7We7kE7InMJTTD7KIeSG/rPp2es4NT3vEveZLgeLGAB6wdY5dgaFaroivETaCqipEOA6JeBhJgE5ps8fIR8F4kt0nWiRs9rX0X1/4FJijopWNsrdBD7w39XDxDnSI/Ki6eGFGs8thP7FAaTgAut4jMg8gJXLqe0Riwqzz7/ha1DuWe32/xACJZs+DR4hrSXyOkwYc75L8HPd1z2CpiU5u2voabN/2PihaTTGZYfmFmxvBhIbW5CJ3oC2CaeXEATapJyh5YPA4vIM2IRCXNp34rCIWG7i7o5nKDUIHLiRrAvQQz6bwsm2kuAAVs86AxEujQ79bY8CwZXBjhWIValVkgQlKa2sH1gfkKTckH0myEk7RJttI7n3AaLEvO/Xj37AVa1uCQYDzKnBeqORW6yhbnAr4UmqQXw4+e9g1XnTgLvF4sRkcqeqvbBCMfEqMPQKUu+ba679ReA5/YdN56E7ywb2g7Zw1UkA1EG9UlACM0xUSMP0UJwHgijEcHpnFaEB8wkdmbrnqnABq1mDIodG7ncHZv+Cn6YGxt5j60KApK72Y+cfhkxZkIWuEfna2c2tx544P163v0oahltI+Be9cFygomImmxxD+WaSnXt2fL/hZLnjPofNLNsvSDTNyrzIYIE6IToztxBu7y0/mBPbRaxDlvuSwgPlepk0JIwLyDjESjBhmvSyPKrVvtothFioLhjn15DndJZ/CyTUfxOj3eeu9QKbVWG+IkpiL73UlfFnL/Y3uAORwj5u2Ax5/FWD8FlWH7bXBcjRIyuJqo1S2ghaiT/UKehoXrZShL5Tjeyw/qDeBivxJsZhJ7SOL0+fr9x2dE6HqhmDiWJ1fdKS9oqstdkUYGDiZZNK9cm+tk3plJcccGggPCBGma4xRxKXTbk+ZnIWu9wSXj+1uG3/+mCfKCv67eVIEHDLmQ8pma3Rm0+ZZJBXNEH+DQ3KGyffL88jINY5JUawCK3+A8XAvRFo8T+u5y4CwF2lwfyddKgJTYG8NAyeIXvor9nS+W2VObMzqbQcz9HmF1BzxsHlU+YCBGMHzu/IwdHaTJqt7A/Nlnzrpgd5f3LKmu9osBP7ms9k3oEeagACF4tf1Af9ySJNB0qkkJFHFNzrTMDwCijtExZ3R7lIjdThyQNmzdqYTE8oxqF8UMC/VB8Z1QTFRy2C0RpB31bHmCVOQSWrYIw7M9QYVeogeFfeju0Oh4w88g= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: fdaad5cd-7566-4a9b-e640-08dce87eae34 X-MS-Exchange-CrossTenant-AuthSource: CH3PR12MB8659.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:23:16.7719 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: tu/QoKBeEhfnrbPFzNBLBXOeGfW+110zvi186QV1iyiwNeRfUD/vW7PhqP66UKjH X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6073 HW with CANWBS is always cache coherent and ignores PCI No Snoop requests as well. This meets the requirement for IOMMU_CAP_ENFORCE_CACHE_COHERENCY, so let's return it. Implement the enforce_cache_coherency() op to reject attaching devices that don't have CANWBS. Reviewed-by: Nicolin Chen Reviewed-by: Mostafa Saleh Tested-by: Nicolin Chen Signed-off-by: Jason Gunthorpe Reviewed-by: Kevin Tian --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 31 +++++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 +++++ 2 files changed, 38 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index acf250aeb18b27..38725810c14eeb 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2293,6 +2293,8 @@ static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap) case IOMMU_CAP_CACHE_COHERENCY: /* Assume that a coherent TCU implies coherent TBUs */ return master->smmu->features & ARM_SMMU_FEAT_COHERENCY; + case IOMMU_CAP_ENFORCE_CACHE_COHERENCY: + return arm_smmu_master_canwbs(master); case IOMMU_CAP_NOEXEC: case IOMMU_CAP_DEFERRED_FLUSH: return true; @@ -2303,6 +2305,26 @@ static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap) } } +static bool arm_smmu_enforce_cache_coherency(struct iommu_domain *domain) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_master_domain *master_domain; + unsigned long flags; + bool ret = true; + + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master_domain, &smmu_domain->devices, + devices_elm) { + if (!arm_smmu_master_canwbs(master_domain->master)) { + ret = false; + break; + } + } + smmu_domain->enforce_cache_coherency = ret; + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + return ret; +} + struct arm_smmu_domain *arm_smmu_domain_alloc(void) { struct arm_smmu_domain *smmu_domain; @@ -2731,6 +2753,14 @@ static int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, * one of them. */ spin_lock_irqsave(&smmu_domain->devices_lock, flags); + if (smmu_domain->enforce_cache_coherency && + !arm_smmu_master_canwbs(master)) { + spin_unlock_irqrestore(&smmu_domain->devices_lock, + flags); + kfree(master_domain); + return -EINVAL; + } + if (state->ats_enabled) atomic_inc(&smmu_domain->nr_ats_masters); list_add(&master_domain->devices_elm, &smmu_domain->devices); @@ -3493,6 +3523,7 @@ static struct iommu_ops arm_smmu_ops = { .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = arm_smmu_attach_dev, + .enforce_cache_coherency = arm_smmu_enforce_cache_coherency, .set_dev_pasid = arm_smmu_s1_set_dev_pasid, .map_pages = arm_smmu_map_pages, .unmap_pages = arm_smmu_unmap_pages, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 1e9952ca989f87..06e3d88932df12 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -811,6 +811,7 @@ struct arm_smmu_domain { /* List of struct arm_smmu_master_domain */ struct list_head devices; spinlock_t devices_lock; + bool enforce_cache_coherency : 1; struct mmu_notifier mmu_notifier; }; @@ -893,6 +894,12 @@ int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq); +static inline bool arm_smmu_master_canwbs(struct arm_smmu_master *master) +{ + return dev_iommu_fwspec_get(master->dev)->flags & + IOMMU_FWSPEC_PCI_RC_CANWBS; +} + #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); bool arm_smmu_master_sva_supported(struct arm_smmu_master *master);