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Wysocki" , Shameerali Kolothum Thodi , Mostafa Saleh Subject: [PATCH v4 04/12] iommu/arm-smmu-v3: Report IOMMU_CAP_ENFORCE_CACHE_COHERENCY for CANWBS Date: Wed, 30 Oct 2024 21:20:48 -0300 Message-ID: <4-v4-9e99b76f3518+3a8-smmuv3_nesting_jgg@nvidia.com> In-Reply-To: <0-v4-9e99b76f3518+3a8-smmuv3_nesting_jgg@nvidia.com> References: X-ClientProxiedBy: BN9PR03CA0286.namprd03.prod.outlook.com (2603:10b6:408:f5::21) To CH3PR12MB8659.namprd12.prod.outlook.com (2603:10b6:610:17c::13) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PR12MB8659:EE_|DM4PR12MB7573:EE_ X-MS-Office365-Filtering-Correlation-Id: 07b97890-df5a-4909-cbab-08dcf941e3d8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|1800799024|921020; X-Microsoft-Antispam-Message-Info: deVc6mg7N5T4meGHVdXtoziRSgqkjsnCooe7d+PAf56e9doBeBaVl8qMCZ8DQIu5PRYbLauqJ22NEa8DbISEmM6hnayK+mRvK+gGQ7VT+f6gn4JYbHp42Lc02j/w3kH0hwXLFlrJEqhZ3rraCNNL8SLgKJSw29y2LaGnx+p5Q8PwwXK8yiS3vaCuc2lyT1VYLOKlWqSk4rwbQEnD5sn4SEIpNeiDeC4abClYtEyYANIgxitAA4Xh2ksHXxfsQwiWHuJU3JIrpIDhQ/hIPy/rzoJ7b+RSl03Ek7iUSNQie5hBCtR9wVm+LoXJwcUtUVbW9IjIPBtR+7XSESaNHCKK8bnIdtblYTReo00pN6bCTt/jxLqGqCT5m+dZb0QNqgwykSkuKUKn2yI5VlfoDDewKi3A7FjE230C+UDjPsLILDyJmhzb7v/3guuObvUPfWg4Knq+jE6jkumKk9DUl6npgwaj9lq6+agwYoBb/4EYbxJEEhFwgrFRUZjHNXKRuKJjaL1nhouk223bLBo21bOu+bT9skV5bib0tFcYCtratJyJeF4dCGEhUAt3HkjqJEB/yESaRHKlTdmstiIpK26432UfkBqyZDDyzFJxHlEDy86p7bp/yjMAK7ydtaCXbFN8dX8WsVhrWwL5ZySpKg41jj5Lizvvx/IFUWurFSkMEpwjt81SBIEq0ZamtpMuKw6xtXPMXxd5a/iG4FraBOA9l7DeNE+SSLlhU3K7zEBeBwOYcQedn8LUjPv0+fcvTl0t/H7GKHf9V7/q2qxEiYbscZPziquzXlnlsCE5+RfLUQlrfMDf5HB3v/3NxviCYCooRzs9omrXniRgMRnVqhI56SXbZ/T08GeI94wX53mVvzN5ilEYIj7sL6wuzf+c04QlRJ18ZVX1dO3K72fTR5hPyrf0U4zTj6XrW4L+99sbJhiak898OEuvtMqj1XrzdUEI13/2pOl6//IRf3Czkf886rPtMkyZHUygLRJBvUEk7RE5yfK0JhwVS8AYa+06gx4zduhTcfSeLsi1uZm3UNQSC1moY0u5AuV7DgA8SHNCAn4xNFADo14H0uH9ha/YzMqxK1zyfg1vcWghGfg8Kn/YGxIeHIqycPCEH0aTjqxPZQyJseO5cwhVz0oK7nwxjV5qh+62/0i0DTuWjrsZ239618K2TNXz/h1+PqYYBRS/WoHEeV1OBUdyIcbK4FyGp1qSQ9ZfO1YNsjdwxQlsKBKmXll1W4r/5MGXZZswryF7rI/GkuSV+eaePqD/fSX/MQmu2d6JaMOx/1c7WNCC8M4XCfsfTIPMpjWa5P257gTnhZJf1pI92zDU7C9ym5GRrk8q1M0meCaSUpyeqTCdKhOTFSL8wPA189yr8s7oJUJzmcY= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH3PR12MB8659.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(7416014)(366016)(1800799024)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Rj6W7zY74x2ubIP4IAKrQfJ/vtkv799UURBb3TVa12gh7sv1KbyEKL1WvFXO7lSDpKEYgMlkOWEWXIiKC8BC6F9LTnWWu70gTPonA/giqCQWoQXbuu4Led1u1m2gcwb6gpt+Mx+2gA7TfmKI30KSrLoP9GX+kxUL0mhhpOFQ4ue/VwnsNPGWnXQUsPHH/VUqLnCa7T2g3sl47EX5Be4zOzmlITr0efb9r6snlFQ/wuz5MP/wcj4SHsxtmoqUqUSIKKOPGLlTq13r8a7AUn940QHAxfguvTuvYtzBY5R45HV4X+tH0FR3ojM14BqHqn8eteVniDn6L5h3qJ2VEIciHX/iJ8vd5lwgrPScGK+TSa5+4XHSmngPbGZbR4KUc4x0q7NbzcvS19Hn/wAyWOKAiZbTp5BKbvWaCjn0BAulOmscpAq9BS71T5xnzIiYPgEoP/gRuCBxsIgPiH8dVPXqI6yJRqZaqvYdlDrqnbuXkOgSOGqnhy3+JW6wjy8damz36CP6lRcYgqCq6zqTyYxkr3kpkoFA0m33heOLtdL+U4K5jg6QWTy+P7c/wxN+fedDZ7lr7ba+zZjdOEv34n4Ykp+yHiPj7ElB7BotjAjbE3bCT7ReLs9ldgPiZJdhuWzrMneNrn55gbIGYM8d406iXC3rMghpamTQaEsEqDfxykN00UNIgNYy1kcZ8zsRa10Xed3Jc8BjD+jZ8LPrdcC8LH0Z7JaMk1xmMoyMlLH4yXs/MRumONXilo5ycdPi5qwaAzRd3BIb8ZctZRtIcpBccpN0vDkz8DV7xyQeWnO0RlG0M1SS7CXZqSabqdxPiU7IH/Ht5Ub0CeHC9UsXEWMSaYnEPVb4JYraFMNjPgRjGkwgqPe4yaWgdoEGIYG4yjr8mzKMpGH9D5JCNA/V1EKjmPeqp/wmklij3WvFXXpmWgMlGV+k9T0HVfODCHrNEXrgCIUppO/UnADPSNqxf2dwQN1ziwu7JhyFNscuYQyrRT9W8SZG7reH0cztpgYecX9QAxM5WVBLyp1WVTGS4T4qZ+hbJCzQ5V13o65vp5DwR5WmKwU6UsUYMYXJgnNYrGt4ZA+U/JwYIhKOYFKIjBpeloMtwiTNtnaPJT5nX6cpTECLWjofU+JAdOBBdEmZ5BZgsji0Y2FPYzVOvGq+dt6bFOW1h0FNGYBwg1b1mjkNn8zmiC68F7Zml9k0VDIgGCGSP52OMUbo9+ENrH70j0QALccCHR5Z0aJ1hmZxQp5Hb+M3D77u4GqNl+B4THj6eS1D42QBQSlAJTeWIGftiO02ZGCsenFMgVUbNjqg0jbx8kVc/t1iWe54fDzenYQ2TgTm8auxvnDDXSndsYDpH8go8FzGaOW8Mqw0ff9QF8oEXiVisVesIBGpQhcrK+FvxKDEwXrL4XN6UUPXbY5SJX7bY1LFOJYrOzvsJwesURFwoASnqwTt4N110owKFTso4gbYZbczvhx3dlq7JXyXSvk3lzwLbSknuVcEc7TRgNIcR2mnBt8lC+PzAneBsk5mlqj8am1n9Igg5DVvyLWjm2L+Vpkcla3cDT2tjBbj18H1qdE= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 07b97890-df5a-4909-cbab-08dcf941e3d8 X-MS-Exchange-CrossTenant-AuthSource: CH3PR12MB8659.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2024 00:20:57.2449 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 5o+YCaV0Gavu1wcfyUBAdVF7INg3D/f9aKASGYS/EaXLpQUz6HjMbvEpB87xfITW X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7573 HW with CANWBS is always cache coherent and ignores PCI No Snoop requests as well. This meets the requirement for IOMMU_CAP_ENFORCE_CACHE_COHERENCY, so let's return it. Implement the enforce_cache_coherency() op to reject attaching devices that don't have CANWBS. Reviewed-by: Nicolin Chen Reviewed-by: Mostafa Saleh Reviewed-by: Kevin Tian Reviewed-by: Jerry Snitselaar Reviewed-by: Donald Dutile Tested-by: Nicolin Chen Signed-off-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 31 +++++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 +++++ 2 files changed, 38 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index acf250aeb18b27..38725810c14eeb 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2293,6 +2293,8 @@ static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap) case IOMMU_CAP_CACHE_COHERENCY: /* Assume that a coherent TCU implies coherent TBUs */ return master->smmu->features & ARM_SMMU_FEAT_COHERENCY; + case IOMMU_CAP_ENFORCE_CACHE_COHERENCY: + return arm_smmu_master_canwbs(master); case IOMMU_CAP_NOEXEC: case IOMMU_CAP_DEFERRED_FLUSH: return true; @@ -2303,6 +2305,26 @@ static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap) } } +static bool arm_smmu_enforce_cache_coherency(struct iommu_domain *domain) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_master_domain *master_domain; + unsigned long flags; + bool ret = true; + + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master_domain, &smmu_domain->devices, + devices_elm) { + if (!arm_smmu_master_canwbs(master_domain->master)) { + ret = false; + break; + } + } + smmu_domain->enforce_cache_coherency = ret; + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + return ret; +} + struct arm_smmu_domain *arm_smmu_domain_alloc(void) { struct arm_smmu_domain *smmu_domain; @@ -2731,6 +2753,14 @@ static int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, * one of them. */ spin_lock_irqsave(&smmu_domain->devices_lock, flags); + if (smmu_domain->enforce_cache_coherency && + !arm_smmu_master_canwbs(master)) { + spin_unlock_irqrestore(&smmu_domain->devices_lock, + flags); + kfree(master_domain); + return -EINVAL; + } + if (state->ats_enabled) atomic_inc(&smmu_domain->nr_ats_masters); list_add(&master_domain->devices_elm, &smmu_domain->devices); @@ -3493,6 +3523,7 @@ static struct iommu_ops arm_smmu_ops = { .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = arm_smmu_attach_dev, + .enforce_cache_coherency = arm_smmu_enforce_cache_coherency, .set_dev_pasid = arm_smmu_s1_set_dev_pasid, .map_pages = arm_smmu_map_pages, .unmap_pages = arm_smmu_unmap_pages, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 1e9952ca989f87..06e3d88932df12 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -811,6 +811,7 @@ struct arm_smmu_domain { /* List of struct arm_smmu_master_domain */ struct list_head devices; spinlock_t devices_lock; + bool enforce_cache_coherency : 1; struct mmu_notifier mmu_notifier; }; @@ -893,6 +894,12 @@ int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq); +static inline bool arm_smmu_master_canwbs(struct arm_smmu_master *master) +{ + return dev_iommu_fwspec_get(master->dev)->flags & + IOMMU_FWSPEC_PCI_RC_CANWBS; +} + #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); bool arm_smmu_master_sva_supported(struct arm_smmu_master *master);