From patchwork Fri Nov 2 08:59:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gerd Hoffmann X-Patchwork-Id: 1687551 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 42B983FE20 for ; Fri, 2 Nov 2012 09:21:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756289Ab2KBJVz (ORCPT ); Fri, 2 Nov 2012 05:21:55 -0400 Received: from mx1.redhat.com ([209.132.183.28]:19923 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752593Ab2KBJVy (ORCPT ); Fri, 2 Nov 2012 05:21:54 -0400 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id qA28xxng021346 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 2 Nov 2012 04:59:59 -0400 Received: from rincewind.home.kraxel.org (ovpn-116-20.ams2.redhat.com [10.36.116.20]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id qA28xtGr018645; Fri, 2 Nov 2012 04:59:56 -0400 Message-ID: <50938B8B.8050804@redhat.com> Date: Fri, 02 Nov 2012 09:59:55 +0100 From: Gerd Hoffmann User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.10) Gecko/20121026 Thunderbird/10.0.10 MIME-Version: 1.0 To: Xudong Hao CC: kevin@koconnor.net, seabios@seabios.org, kvm@vger.kernel.org, avi@redhat.com Subject: Re: [PATCH] seabios/pci: enable 64 bit bar on seabios References: <1351834928-25975-1-git-send-email-xudong.hao@intel.com> In-Reply-To: <1351834928-25975-1-git-send-email-xudong.hao@intel.com> X-Enigmail-Version: 1.4 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.25 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 11/02/12 06:42, Xudong Hao wrote: > 64 bit bar sizing and MMIO allocation. The 64 bit window is placed above high > memory, top down from the end of guest physical address space. What problem you are trying to fix? The existing code should handle 64bit bars just fine. By default they are placed below 4G though for compatibility reasons (make old 32bit guests happy). When running out of address space seabios will try map them above 4G though to make room below 4G. Mapping your 64bit PCI bars above 4G unconditionally (for testing or other reasons) can simply be done this way: We might want add a config option for this. cheers, Gerd --- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- a/src/pciinit.c +++ b/src/pciinit.c @@ -599,7 +599,7 @@ static void pci_bios_map_devices(struct pci_bus *busses) { pcimem_start = RamSize; - if (pci_bios_init_root_regions(busses)) { + if (1 /* pci_bios_init_root_regions(busses) */) { struct pci_region r64_mem, r64_pref; r64_mem.list = NULL; r64_pref.list = NULL;