From patchwork Fri Feb 3 15:59:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 9554605 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 500F0604A7 for ; Fri, 3 Feb 2017 16:02:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 23C5527F80 for ; Fri, 3 Feb 2017 16:02:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 17E2B27D85; Fri, 3 Feb 2017 16:02:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7A66A27D85 for ; Fri, 3 Feb 2017 16:02:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751026AbdBCQCA (ORCPT ); Fri, 3 Feb 2017 11:02:00 -0500 Received: from foss.arm.com ([217.140.101.70]:53432 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750828AbdBCQBo (ORCPT ); Fri, 3 Feb 2017 11:01:44 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 59BF6707; Fri, 3 Feb 2017 08:00:50 -0800 (PST) Received: from [10.1.206.46] (melchizedek.cambridge.arm.com [10.1.206.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CE76E3F220; Fri, 3 Feb 2017 08:00:43 -0800 (PST) Message-ID: <5894A8E5.6000803@arm.com> Date: Fri, 03 Feb 2017 15:59:33 +0000 From: James Morse User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.6.0 MIME-Version: 1.0 To: Tyler Baicar CC: christoffer.dall@linaro.org, marc.zyngier@arm.com, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, rjw@rjwysocki.net, lenb@kernel.org, matt@codeblueprint.co.uk, robert.moore@intel.com, lv.zheng@intel.com, nkaje@codeaurora.org, zjzhang@codeaurora.org, mark.rutland@arm.com, akpm@linux-foundation.org, eun.taik.lee@samsung.com, sandeepa.s.prabhu@gmail.com, labbott@redhat.com, shijie.huang@arm.com, rruigrok@codeaurora.org, paul.gortmaker@windriver.com, tn@semihalf.com, fu.wei@linaro.org, rostedt@goodmis.org, bristot@redhat.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org, devel@acpica.org, Suzuki.Poulose@arm.com, punit.agrawal@arm.com, astone@redhat.com, harba@codeaurora.org, hanjun.guo@linaro.org, john.garry@huawei.com, shiju.jose@huawei.com Subject: Re: [PATCH V8 04/10] arm64: exception: handle Synchronous External Abort References: <1485969413-23577-1-git-send-email-tbaicar@codeaurora.org> <1485969413-23577-5-git-send-email-tbaicar@codeaurora.org> In-Reply-To: <1485969413-23577-5-git-send-email-tbaicar@codeaurora.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Tyler, On 01/02/17 17:16, Tyler Baicar wrote: > SEA exceptions are often caused by an uncorrected hardware > error, and are handled when data abort and instruction abort > exception classes have specific values for their Fault Status > Code. > When SEA occurs, before killing the process, report the error > in the kernel logs. > Update fault_info[] with specific SEA faults so that the > new SEA handler is used. > diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c > index 156169c..9ae7e65 100644 > --- a/arch/arm64/mm/fault.c > +++ b/arch/arm64/mm/fault.c > @@ -487,6 +487,31 @@ static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs) > return 1; > } > > +#define SEA_FnV_MASK 0x00000400 There are a glut of ESR_ELx_ macros in arch/arm64/include/asm/esr.h, could this be fitted in there in a similar format? > + > +/* > + * This abort handler deals with Synchronous External Abort. > + * It calls notifiers, and then returns "fault". > + */ > +static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) > +{ > + struct siginfo info; > + > + pr_err("Synchronous External Abort: %s (0x%08x) at 0x%016lx\n", > + fault_name(esr), esr, addr); > + > + info.si_signo = SIGBUS; > + info.si_errno = 0; > + info.si_code = 0; > + if (esr & SEA_FnV_MASK) > + info.si_addr = 0; > + else > + info.si_addr = (void __user *)addr; > + arm64_notify_die("", regs, &info, esr); > + > + return 0; > +} > + > static const struct fault_info { > int (*fn)(unsigned long addr, unsigned int esr, struct pt_regs *regs); > int sig; > @@ -509,22 +534,22 @@ static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs) > { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" }, > { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" }, > { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" }, > - { do_bad, SIGBUS, 0, "synchronous external abort" }, > + { do_sea, SIGBUS, 0, "synchronous external abort" }, This will print: > Synchronous External Abort: synchronous external abort It looks odd, but I can't think of anything better to put there. > { do_bad, SIGBUS, 0, "unknown 17" }, > { do_bad, SIGBUS, 0, "unknown 18" }, > { do_bad, SIGBUS, 0, "unknown 19" }, > - { do_bad, SIGBUS, 0, "synchronous external abort (translation table walk)" }, > - { do_bad, SIGBUS, 0, "synchronous external abort (translation table walk)" }, > - { do_bad, SIGBUS, 0, "synchronous external abort (translation table walk)" }, > - { do_bad, SIGBUS, 0, "synchronous external abort (translation table walk)" }, > - { do_bad, SIGBUS, 0, "synchronous parity error" }, > + { do_sea, SIGBUS, 0, "level 0 (translation table walk)" }, > + { do_sea, SIGBUS, 0, "level 1 (translation table walk)" }, > + { do_sea, SIGBUS, 0, "level 2 (translation table walk)" }, > + { do_sea, SIGBUS, 0, "level 3 (translation table walk)" }, > + { do_sea, SIGBUS, 0, "synchronous parity or ECC error" }, > { do_bad, SIGBUS, 0, "unknown 25" }, > { do_bad, SIGBUS, 0, "unknown 26" }, > { do_bad, SIGBUS, 0, "unknown 27" }, > - { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk)" }, > - { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk)" }, > - { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk)" }, > - { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk)" }, > + { do_sea, SIGBUS, 0, "level 0 synchronous parity error (translation table walk)" }, > + { do_sea, SIGBUS, 0, "level 1 synchronous parity error (translation table walk)" }, > + { do_sea, SIGBUS, 0, "level 2 synchronous parity error (translation table walk)" }, > + { do_sea, SIGBUS, 0, "level 3 synchronous parity error (translation table walk)" }, > { do_bad, SIGBUS, 0, "unknown 32" }, > { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" }, > { do_bad, SIGBUS, 0, "unknown 34" }, > With the ESR_ELx_FnV change above, Reviewed-by: James Morse Thanks, James --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -83,6 +83,7 @@ #define ESR_ELx_WNR (UL(1) << 6) /* Shared ISS field definitions for Data/Instruction aborts */ +#define ESR_ELx_FnV (UL(1) << 10) #define ESR_ELx_EA (UL(1) << 9) #define ESR_ELx_S1PTW (UL(1) << 7)