From patchwork Tue Dec 12 09:31:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xu, Haibo1" X-Patchwork-Id: 13488772 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="O0O4Qvy5" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8EFB11F; Tue, 12 Dec 2023 01:20:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702372844; x=1733908844; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bCbMxYqsNc6ysevtODH1LdEzA9cmGSP1KVajSHQPjJU=; b=O0O4Qvy55ltuH81dmJRHwdGmihtcQp/Ng3l++Uawa1rpksLfyYAkXxj9 EgAb9RoJnl5GVu+84A7tA0p3BmdamG6b4Hs+JOO5ANjRXU5AUNjygSTVh UzT9GNB02HEnNYCl42R2IEfWrKoofeCSnklq9WXhO/bfBz2IGPmBieF0x aclSL7wtjxGhXC+bW1s8+IEI/Jb1hOaUembStnIVomlkQv19byO8FV6JU H6YpW32UcFwzWa88kjmZT+EptnYxtJ3+kp/YLHxG8X3zz94Azh2uRUAms z/2EkubTxYr/1grp1Ijzw33I528wht2+OUcfN3xN/X7Xi4/wNTxVjvJiB Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10921"; a="480974352" X-IronPort-AV: E=Sophos;i="6.04,269,1695711600"; d="scan'208";a="480974352" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2023 01:20:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10921"; a="917213171" X-IronPort-AV: E=Sophos;i="6.04,269,1695711600"; d="scan'208";a="917213171" Received: from haibo-optiplex-7090.sh.intel.com ([10.239.159.132]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2023 01:20:36 -0800 From: Haibo Xu To: Cc: xiaobo55x@gmail.com, haibo1.xu@intel.com, ajones@ventanamicro.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Anup Patel , Atish Patra , Guo Ren , Mayuresh Chitale , Daniel Henrique Barboza , wchen , Conor Dooley , Minda Chen , Heiko Stuebner , Jisheng Zhang , Samuel Holland , Sean Christopherson , Like Xu , Peter Xu , Vipin Sharma , Aaron Lewis , Maciej Wieczor-Retman , Thomas Huth , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm-riscv@lists.infradead.org Subject: [PATCH v4 06/11] KVM: riscv: selftests: Switch to use macro from csr.h Date: Tue, 12 Dec 2023 17:31:15 +0800 Message-Id: <5f5f837cd052587f1d49f81a2c4dc58a5330fe47.1702371136.git.haibo1.xu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Signed-off-by: Haibo Xu Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/include/riscv/processor.h | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h index 5b62a3d2aa9b..6f9e1e5e466d 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -7,8 +7,9 @@ #ifndef SELFTEST_KVM_PROCESSOR_H #define SELFTEST_KVM_PROCESSOR_H -#include "kvm_util.h" #include +#include +#include "kvm_util.h" static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx, uint64_t size) @@ -95,13 +96,6 @@ static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx, #define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE #define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT -#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) -#define SATP_MODE_39 _AC(0x8000000000000000, UL) -#define SATP_MODE_48 _AC(0x9000000000000000, UL) -#define SATP_ASID_BITS 16 -#define SATP_ASID_SHIFT 44 -#define SATP_ASID_MASK _AC(0xFFFF, UL) - #define SBI_EXT_EXPERIMENTAL_START 0x08000000 #define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF