From patchwork Thu Sep 14 01:36:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xu, Haibo1" X-Patchwork-Id: 13383955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 143DDEE0203 for ; Thu, 14 Sep 2023 01:29:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233777AbjINB3R (ORCPT ); Wed, 13 Sep 2023 21:29:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233804AbjINB3O (ORCPT ); Wed, 13 Sep 2023 21:29:14 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4409D1BE4; Wed, 13 Sep 2023 18:29:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1694654950; x=1726190950; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HECq7ZimFQCzoaZmWYi01Qtb1SUQg3CL84moiHOKq74=; b=n7GC/auuc+/yvIFgoHDSBiwTV6O2wRq6ByP97cti2XeceP+9UTQt+Jw5 xwxY01BeTzB1VnO26uvEMmgCFyI3QyznECE1Bo/ZgLsco+SWTfZg/ksuO lMDtXDHIL+uk0nIdBTAnRQykqmKQbeUwsUpptF5rMJquS/3XxckqzfSt0 S79XI3AsLrlm/NeD/5hpqwNILQ32+Ez4Cif7LRUJtDG5lHUJ9UTyXRrxm mF3OzvugZ5VMEePKcRQhJk2GqfsX+NTuAD63GZE3bqlN3JUjCDadqFjml uINx/hxdtXnTIXf9TWJfbtJJiLMOEZ7YYqG+v+GmC6oWIQ1+cQu5YploB w==; X-IronPort-AV: E=McAfee;i="6600,9927,10832"; a="377734170" X-IronPort-AV: E=Sophos;i="6.02,144,1688454000"; d="scan'208";a="377734170" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2023 18:29:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10832"; a="694049382" X-IronPort-AV: E=Sophos;i="6.02,144,1688454000"; d="scan'208";a="694049382" Received: from haibo-optiplex-7090.sh.intel.com ([10.239.159.132]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2023 18:29:02 -0700 From: Haibo Xu Cc: xiaobo55x@gmail.com, haibo1.xu@intel.com, ajones@ventanamicro.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Anup Patel , Atish Patra , Sean Christopherson , Ricardo Koller , Vishal Annapurve , Peter Xu , Vipin Sharma , David Matlack , Colton Lewis , Aaron Lewis , Thomas Huth , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm-riscv@lists.infradead.org Subject: [PATCH v3 5/9] KVM: riscv: selftests: Switch to use macro from csr.h Date: Thu, 14 Sep 2023 09:36:59 +0800 Message-Id: <6cdda82518977c67004ee01a767bc67962352c13.1694421911.git.haibo1.xu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Haibo Xu Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/include/riscv/processor.h | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h index 5b62a3d2aa9b..67766baed4f7 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -8,6 +8,7 @@ #define SELFTEST_KVM_PROCESSOR_H #include "kvm_util.h" +#include #include static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx, @@ -95,13 +96,6 @@ static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx, #define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE #define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT -#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) -#define SATP_MODE_39 _AC(0x8000000000000000, UL) -#define SATP_MODE_48 _AC(0x9000000000000000, UL) -#define SATP_ASID_BITS 16 -#define SATP_ASID_SHIFT 44 -#define SATP_ASID_MASK _AC(0xFFFF, UL) - #define SBI_EXT_EXPERIMENTAL_START 0x08000000 #define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF