From patchwork Tue Mar 31 07:32:05 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dong, Eddie" X-Patchwork-Id: 15333 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n2V7XfFE000384 for ; Tue, 31 Mar 2009 07:33:41 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755369AbZCaHda (ORCPT ); Tue, 31 Mar 2009 03:33:30 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1754759AbZCaHd3 (ORCPT ); Tue, 31 Mar 2009 03:33:29 -0400 Received: from mga09.intel.com ([134.134.136.24]:50443 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752625AbZCaHd2 (ORCPT ); Tue, 31 Mar 2009 03:33:28 -0400 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 31 Mar 2009 00:24:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.38,451,1233561600"; d="scan'208";a="398972367" Received: from pgsmsx602.gar.corp.intel.com ([10.221.43.81]) by orsmga002.jf.intel.com with ESMTP; 31 Mar 2009 00:41:43 -0700 Received: from pgsmsx601.gar.corp.intel.com (10.221.43.69) by pgsmsx602.gar.corp.intel.com (10.221.43.81) with Microsoft SMTP Server (TLS) id 8.1.340.0; Tue, 31 Mar 2009 15:32:07 +0800 Received: from pdsmsx602.ccr.corp.intel.com (172.16.12.184) by pgsmsx601.gar.corp.intel.com (10.221.43.69) with Microsoft SMTP Server (TLS) id 8.1.340.0; Tue, 31 Mar 2009 15:32:06 +0800 Received: from pdsmsx503.ccr.corp.intel.com ([172.16.12.95]) by pdsmsx602.ccr.corp.intel.com ([172.16.12.184]) with mapi; Tue, 31 Mar 2009 15:32:05 +0800 From: "Dong, Eddie" To: Avi Kivity CC: "kvm@vger.kernel.org" , "Neiger, Gil" , "Dong, Eddie" Date: Tue, 31 Mar 2009 15:32:05 +0800 Subject: RE: Use rsvd_bits_mask in load_pdptrs for cleanup and considing EXB bit Thread-Topic: Use rsvd_bits_mask in load_pdptrs for cleanup and considing EXB bit Thread-Index: AcmxMPTRiTh1NecdR4KRQzazpFjVZAAaYxLQAAb477AABwedcA== Message-ID: <9832F13BD22FB94A829F798DA4A8280501A3C029EB@pdsmsx503.ccr.corp.intel.com> References: <9832F13BD22FB94A829F798DA4A8280501A3C02542@pdsmsx503.ccr.corp.intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Neiger, Gil wrote: > PDPTEs are used only if CR0.PG=CR4.PAE=1. > > In that situation, their format depends the value of IA32_EFER.LMA. > > If IA32_EFER.LMA=0, bit 63 is reserved and must be 0 in any PDPTE > that is marked present. The execute-disable setting of a page is > determined only by the PDE and PTE. > > If IA32_EFER.LMA=1, bit 63 is used for the execute-disable in PML4 > entries, PDPTEs, PDEs, and PTEs (assuming IA32_EFER.NXE=1). > > - Gil Rebased. Thanks, eddie commit 032caed3da123950eeb3e192baf444d4eae80c85 Author: root Date: Tue Mar 31 16:22:49 2009 +0800 Use rsvd_bits_mask in load_pdptrs and remove bit 5-6 from rsvd_bits_mask per latest SDM. Signed-off-by: Eddie Dong diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 2eab758..1bed3aa 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -225,11 +225,6 @@ static int is_nx(struct kvm_vcpu *vcpu) return vcpu->arch.shadow_efer & EFER_NX; } -static int is_present_pte(unsigned long pte) -{ - return pte & PT_PRESENT_MASK; -} - static int is_shadow_present_pte(u64 pte) { return pte != shadow_trap_nonpresent_pte @@ -2199,6 +2194,9 @@ void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) context->rsvd_bits_mask[1][0] = 0; break; case PT32E_ROOT_LEVEL: + context->rsvd_bits_mask[0][2] = + rsvd_bits(maxphyaddr, 63) | + rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ context->rsvd_bits_mask[0][1] = exb_bit_rsvd | rsvd_bits(maxphyaddr, 62); /* PDE */ context->rsvd_bits_mask[0][0] = exb_bit_rsvd | diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h index 258e5d5..2a6eb50 100644 --- a/arch/x86/kvm/mmu.h +++ b/arch/x86/kvm/mmu.h @@ -75,4 +75,9 @@ static inline int is_paging(struct kvm_vcpu *vcpu) return vcpu->arch.cr0 & X86_CR0_PG; } +static inline int is_present_pte(unsigned long pte) +{ + return pte & PT_PRESENT_MASK; +} + #endif diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 961bd2b..b449ff0 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -233,7 +233,8 @@ int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) goto out; } for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { - if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) { + if (is_present_pte(pdpte[i]) && + (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { ret = 0; goto out; }