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Wed, 21 Mar 2018 15:58:43 +0000 Received: from CY4PR12MB1768.namprd12.prod.outlook.com ([fe80::4873:8395:24d2:8f6f]) by CY4PR12MB1768.namprd12.prod.outlook.com ([fe80::4873:8395:24d2:8f6f%13]) with mapi id 15.20.0588.017; Wed, 21 Mar 2018 15:58:42 +0000 From: "Moger, Babu" To: Eduardo Habkost CC: "pbonzini@redhat.com" , "rth@twiddle.net" , "rkrcmar@redhat.com" , "Lendacky, Thomas" , "Singh, Brijesh" , "kvm@vger.kernel.org" , "kash@tripleback.net" , "mtosatti@redhat.com" , "Hook, Gary" , "qemu-devel@nongnu.org" Subject: RE: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information Thread-Topic: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information Thread-Index: AQHTukVEzswBDyNvAUGstQjCrQTsIaPTLLAAgAY8/jCAAArBgIABcFmg Date: Wed, 21 Mar 2018 15:58:41 +0000 Message-ID: References: <1520888449-4352-1-git-send-email-babu.moger@amd.com> <1520888449-4352-3-git-send-email-babu.moger@amd.com> <20180316180006.GH28578@localhost.localdomain> <20180320175427.GU3417@localhost.localdomain> In-Reply-To: <20180320175427.GU3417@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; 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BCL:0; PCL:0; RULEID:; SRVR:CY4PR12MB1832; x-forefront-prvs: 0618E4E7E1 received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: cUog0fJ6vNgrHXXHJrDbIp9/eulgzXNK5SZaRbfXThgo/C1qAJuEaNWTJverBskgB2HOyZDTgIzWuKTedjUdgl2PTofOtJkOVxnF5kc2xxmeDzIs+0IrMku1h9eZDsBN/s8XuG0aYXasNFFzjYjK/VwokaUI1AsLvIsDSrHbHdSJzG+eycaF+8sffOpW0CvY+KUXu/GTwbH7bomr238gLLltw3f3ZZQn+BIKmNobzCpR1GVzIYkm9LFXFHTVeRobWou9ztRkGo21yU81p9nawNvy85jjh+s25FpdULrfsob9Ya5XvzJLJzB7O8Kl6h0ReCmK45b3AvdyHypr+ogJyA== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8d6b9cf4-0fcb-4724-680f-08d58f449e62 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Mar 2018 15:58:41.9184 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1832 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Eduardo, > -----Original Message----- > From: Eduardo Habkost > Sent: Tuesday, March 20, 2018 12:54 PM > To: Moger, Babu > Cc: pbonzini@redhat.com; rth@twiddle.net; rkrcmar@redhat.com; > Lendacky, Thomas ; Singh, Brijesh > ; kvm@vger.kernel.org; kash@tripleback.net; > mtosatti@redhat.com; Hook, Gary ; qemu- > devel@nongnu.org > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD > Processor Cache Information > > On Tue, Mar 20, 2018 at 05:25:52PM +0000, Moger, Babu wrote: > > Hi Eduardo, Thanks for the comments. Please see the response inline. > > > > > -----Original Message----- > > > From: Eduardo Habkost > > > Sent: Friday, March 16, 2018 1:00 PM > > > To: Moger, Babu > > > Cc: pbonzini@redhat.com; rth@twiddle.net; rkrcmar@redhat.com; > > > Lendacky, Thomas ; Singh, Brijesh > > > ; kvm@vger.kernel.org; kash@tripleback.net; > > > mtosatti@redhat.com; Hook, Gary ; qemu- > > > devel@nongnu.org > > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD > > > Processor Cache Information > > > > > > On Mon, Mar 12, 2018 at 05:00:46PM -0400, Babu Moger wrote: > > > > From: Stanislav Lanci > > > > > > > > Add information for cpuid 0x8000001D leaf. Populate cache topology > > > information > > > > for different cache types(Data Cache, Instruction Cache, L2 and L3) > > > supported > > > > by 0x8000001D leaf. Please refer Processor Programming Reference > (PPR) > > > for AMD > > > > Family 17h Model for more details. > > > > > > > > Signed-off-by: Stanislav Lanci > > > > Signed-off-by: Babu Moger > > > > > > The new CPUID leaves don't seem to match the existing AMD cache > > > information > > > leaves. Is this intentional? Why? > > > > It is not intentional. These values are from older family of processors. > These values have changed from Family 14 or later. > > The latest one is Family 17. You can see the differences here. > > https://support.amd.com/TechDocs/41131.pdf > > > https://support.amd.com/TechDocs/55072_AMD_Family_15h_Models_70h- > 7Fh_BKDG.pdf > > > https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h- > 0Fh.pdf > > > > Some of these are bugs in our code. For some we need to add checks for > the family and correct these values. > > You understand the code much better than me. Correct me if I missed > something. > > > > Note that older family of processors don't support topology extensions. > > If you want to make the cache size/topology look different > depending on the CPU model/options, this would require more work, > but it would be an interesting feature. > > The "i386: Helpers to encode cache information consistently" > patch I sent last week might be a useful starting point for that. > > If you plan to implement that, please keep in mind that existing > CPUID cache info needs to be kept on previous machine-types (this > is implemented by adding QOM properties that can be used to > enable the old behavior, and by setting them at > MachineClass::compat_props). Wanted to get some confirmation what you meant by setting MachineClass::compat_props. Here is the patch I created to add new property for cpu. Now, I can use enable_topoext to display new change properly based on family. Is that what you meant ? > > -- > Eduardo diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index ffee841..d1ee053 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -369,6 +369,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); HW_COMPAT_2_7 \ {\ .driver = TYPE_X86_CPU,\ + .property = "topoext",\ + .value = "off",\ + },\ + {\ + .driver = TYPE_X86_CPU,\ .property = "l3-cache",\ .value = "off",\ },\ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 84d64de..557a2d6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5080,6 +5080,7 @@ static Property x86_cpu_properties[] = { false), DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), + DEFINE_PROP_BOOL("topoext", X86CPU, enable_topoext, true), /* * From "Requirements for Implementing the Microsoft diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 2e2bab5..3d3caa1 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1333,6 +1333,11 @@ struct X86CPU { */ bool enable_l3_cache; + /* Compatibility bits for old machine types. + * If true present the new cache topology information + */ + bool enable_topoext; + /* Compatibility bits for old machine types: */ bool enable_cpuid_0xb;