From patchwork Fri Nov 29 13:17:43 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Jinsong" X-Patchwork-Id: 3258241 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 92E659F384 for ; Fri, 29 Nov 2013 13:17:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D227220671 for ; Fri, 29 Nov 2013 13:17:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9BAC02066D for ; Fri, 29 Nov 2013 13:17:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755370Ab3K2NRt (ORCPT ); Fri, 29 Nov 2013 08:17:49 -0500 Received: from mga11.intel.com ([192.55.52.93]:40983 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753440Ab3K2NRs convert rfc822-to-8bit (ORCPT ); Fri, 29 Nov 2013 08:17:48 -0500 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 29 Nov 2013 05:17:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.93,798,1378882800"; d="scan'208,223";a="442023061" Received: from fmsmsx105.amr.corp.intel.com ([10.19.9.36]) by fmsmga002.fm.intel.com with ESMTP; 29 Nov 2013 05:17:46 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX105.amr.corp.intel.com (10.19.9.36) with Microsoft SMTP Server (TLS) id 14.3.123.3; Fri, 29 Nov 2013 05:17:46 -0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.57]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.235]) with mapi id 14.03.0123.003; Fri, 29 Nov 2013 21:17:44 +0800 From: "Liu, Jinsong" To: Paolo Bonzini , Gleb Natapov , "qemu-devel@nongnu.org" , kvm CC: "haoxudong.hao@gmail.com" Subject: [PATCH 2/2] target-i386: Intel MPX support Thread-Topic: [PATCH 2/2] target-i386: Intel MPX support Thread-Index: Ac7tBWN96Ga8TgDCQpCXkNGmHodM3A== Date: Fri, 29 Nov 2013 13:17:43 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From aac033473bc88befe39a9add99820c0a7118ac90 Mon Sep 17 00:00:00 2001 From: root Date: Fri, 22 Nov 2013 00:24:35 +0800 Subject: [PATCH 2/2] target-i386: Intel MPX support Expose cpuid leaf (0xd, 3) and (0xd, 4) to guest. Fix ebx and re-calculate ecx of cpuid leaf (0xd, 0). Signed-off-by: Liu Jinsong --- target-i386/cpu.c | 34 ++++++++++++++++++++++++++-------- target-i386/cpu.h | 1 + 2 files changed, 27 insertions(+), 8 deletions(-) -- 1.7.1-- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 544b57f..7d04f28 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -330,12 +330,12 @@ X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { typedef struct ExtSaveArea { uint32_t feature, bits; - uint32_t offset, size; } ExtSaveArea; static const ExtSaveArea ext_save_areas[] = { - [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, - .offset = 0x240, .size = 0x100 }, + [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX }, + [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX }, + [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX }, }; const char *get_register_name_32(unsigned int reg) @@ -2204,9 +2204,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32); if (count == 0) { - *ecx = 0x240; + *ebx = *ecx = 0x240; for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) { + uint32_t offset, size; const ExtSaveArea *esa = &ext_save_areas[i]; + if ((env->features[esa->feature] & esa->bits) == esa->bits && (kvm_mask & (1 << i)) != 0) { if (i < 32) { @@ -2214,19 +2216,35 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, } else { *edx |= 1 << (i - 32); } - *ecx = MAX(*ecx, esa->offset + esa->size); + + size = kvm_arch_get_supported_cpuid(s, 0xd, i, R_EAX); + offset = kvm_arch_get_supported_cpuid(s, 0xd, i, R_EBX); + *ecx = MAX(*ecx, offset + size); + + /* + * EBX here just in order to + * 1. keep compatible with old qemu version, take AVX + * into account; + * 2. keep compatible with old kernel version. Currently + * KVM has bug when expose cpuid 0xd to guest (include + * static value when guest booting and dynamic value + * when guest enables XCR0 features. EBX here can + * co-work with old buggy and new updated KVM, keep + * same value independent to CPU and kernel version. + */ + if (i == 2) + *ebx = MAX(*ebx, offset + size); } } *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE); - *ebx = *ecx; } else if (count == 1) { *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX); } else if (count < ARRAY_SIZE(ext_save_areas)) { const ExtSaveArea *esa = &ext_save_areas[count]; if ((env->features[esa->feature] & esa->bits) == esa->bits && (kvm_mask & (1 << count)) != 0) { - *eax = esa->size; - *ebx = esa->offset; + *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX); + *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX); } } break; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index ea373e8..9a838d1 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -545,6 +545,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EBX_ERMS (1 << 9) #define CPUID_7_0_EBX_INVPCID (1 << 10) #define CPUID_7_0_EBX_RTM (1 << 11) +#define CPUID_7_0_EBX_MPX (1 << 14) #define CPUID_7_0_EBX_RDSEED (1 << 18) #define CPUID_7_0_EBX_ADX (1 << 19) #define CPUID_7_0_EBX_SMAP (1 << 20)