From patchwork Mon May 15 21:27:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tyler Baicar X-Patchwork-Id: 9728035 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3EB776028A for ; Mon, 15 May 2017 21:30:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 46624289D7 for ; Mon, 15 May 2017 21:30:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 44743289DC; Mon, 15 May 2017 21:30:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A0603289DA for ; Mon, 15 May 2017 21:30:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934204AbdEOV3H (ORCPT ); Mon, 15 May 2017 17:29:07 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:50276 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933943AbdEOV3C (ORCPT ); Mon, 15 May 2017 17:29:02 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 13C3E60DB6; Mon, 15 May 2017 21:28:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1494883736; bh=jJYDjmZ1VjODLPaFpOE3BnR/nKtmYRxi2vtcS5fD0fI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Vk+gbq7c9GtEiozQ2Wa0aFVGsH/zDhphdUet39cq2Q1L0H8uB3n8FTxI+ezof6b/Z znlU4MVwHQ2a5iQVHAyo/PGS4LVoFsYJZcm5gxqzRgWXkAZfD5DwhQPjokCfc+I5pV L+K5szs3nOh7RdNE1zHaF9xkByHx1paAvVbACrGs= Received: from tbaicar-lnx.qualcomm.com (unknown [129.46.14.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: tbaicar@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1860D60DA7; Mon, 15 May 2017 21:28:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1494883731; bh=jJYDjmZ1VjODLPaFpOE3BnR/nKtmYRxi2vtcS5fD0fI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j8M3IWMeMUV4+UyPOjJz5Zqa0YWSE9tuwrJruzlce0KMLrdL1MfO1yXDzp/cmi9nX nKdachkTJCzNd8AlbvMz35iBc5nUY/KnVp/Efl1j24qByIfeSk1IG3FasdU+LAK3xc 71H4Hc9Rhv480KUTdVqSyVcHALMS3pShZkqNuIyg= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1860D60DA7 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=tbaicar@codeaurora.org From: Tyler Baicar To: christoffer.dall@linaro.org, marc.zyngier@arm.com, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, rjw@rjwysocki.net, lenb@kernel.org, matt@codeblueprint.co.uk, robert.moore@intel.com, lv.zheng@intel.com, nkaje@codeaurora.org, zjzhang@codeaurora.org, mark.rutland@arm.com, james.morse@arm.com, akpm@linux-foundation.org, eun.taik.lee@samsung.com, sandeepa.s.prabhu@gmail.com, labbott@redhat.com, shijie.huang@arm.com, rruigrok@codeaurora.org, paul.gortmaker@windriver.com, tn@semihalf.com, fu.wei@linaro.org, rostedt@goodmis.org, bristot@redhat.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org, Suzuki.Poulose@arm.com, punit.agrawal@arm.com, astone@redhat.com, harba@codeaurora.org, hanjun.guo@linaro.org, john.garry@huawei.com, shiju.jose@huawei.com, joe@perches.com, bp@alien8.de, rafael@kernel.org, tony.luck@intel.com, gengdongjiu@huawei.com, xiexiuqi@huawei.com Cc: Tyler Baicar Subject: [PATCH V16 10/11] trace, ras: add ARM processor error trace event Date: Mon, 15 May 2017 15:27:59 -0600 Message-Id: <1494883680-25551-11-git-send-email-tbaicar@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1494883680-25551-1-git-send-email-tbaicar@codeaurora.org> References: <1494883680-25551-1-git-send-email-tbaicar@codeaurora.org> Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Currently there are trace events for the various RAS errors with the exception of ARM processor type errors. Add a new trace event for such errors so that the user will know when they occur. These trace events are consistent with the ARM processor error section type defined in UEFI 2.6 spec section N.2.4.4. Signed-off-by: Tyler Baicar Acked-by: Steven Rostedt Reviewed-by: Xie XiuQi --- drivers/acpi/apei/ghes.c | 6 +++++- drivers/firmware/efi/cper.c | 1 + drivers/ras/ras.c | 6 ++++++ include/linux/ras.h | 3 +++ include/ras/ras_event.h | 45 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 1106722..2dddb3b 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -518,7 +518,11 @@ static void ghes_do_proc(struct ghes *ghes, } #endif - else { + else if (!uuid_le_cmp(sec_type, CPER_SEC_PROC_ARM)) { + struct cper_sec_proc_arm *err = acpi_hest_get_payload(gdata); + + call_arm_trace_event(err); + } else { void *err = acpi_hest_get_payload(gdata); call_non_standard_trace_event(&sec_type, fru_id, diff --git a/drivers/firmware/efi/cper.c b/drivers/firmware/efi/cper.c index d5a5855..48a8f69 100644 --- a/drivers/firmware/efi/cper.c +++ b/drivers/firmware/efi/cper.c @@ -35,6 +35,7 @@ #include #include #include +#include #define INDENT_SP " " diff --git a/drivers/ras/ras.c b/drivers/ras/ras.c index 57363be..8655ef4 100644 --- a/drivers/ras/ras.c +++ b/drivers/ras/ras.c @@ -20,6 +20,11 @@ void call_non_standard_trace_event(const uuid_le *sec_type, trace_non_standard_event(sec_type, fru_id, fru_text, sev, err, len); } +void call_arm_trace_event(struct cper_sec_proc_arm *err) +{ + trace_arm_event(err); +} + static int __init ras_init(void) { int rc = 0; @@ -36,3 +41,4 @@ static int __init ras_init(void) #endif EXPORT_TRACEPOINT_SYMBOL_GPL(mc_event); EXPORT_TRACEPOINT_SYMBOL_GPL(non_standard_event); +EXPORT_TRACEPOINT_SYMBOL_GPL(arm_event); diff --git a/include/linux/ras.h b/include/linux/ras.h index 7d397a1..988e3ac 100644 --- a/include/linux/ras.h +++ b/include/linux/ras.h @@ -2,6 +2,7 @@ #define __RAS_H__ #include +#include #ifdef CONFIG_DEBUG_FS int ras_userspace_consumers(void); @@ -17,10 +18,12 @@ void call_non_standard_trace_event(const uuid_le *sec_type, const uuid_le *fru_id, const char *fru_text, const u8 sev, const u8 *err, const u32 len); +void call_arm_trace_event(struct cper_sec_proc_arm *err); #else static void call_non_standard_trace_event(const uuid_le *sec_type, const uuid_le *fru_id, const char *fru_text, const u8 sev, const u8 *err, const u32 len) { return; } +static void call_arm_trace_event(struct cper_sec_proc_arm *err) { return; } #endif #endif diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h index 4f79ba9..429f46f 100644 --- a/include/ras/ras_event.h +++ b/include/ras/ras_event.h @@ -162,6 +162,51 @@ ); /* + * ARM Processor Events Report + * + * This event is generated when hardware detects an ARM processor error + * has occurred. UEFI 2.6 spec section N.2.4.4. + */ +TRACE_EVENT(arm_event, + + TP_PROTO(const struct cper_sec_proc_arm *proc), + + TP_ARGS(proc), + + TP_STRUCT__entry( + __field(u64, mpidr) + __field(u64, midr) + __field(u32, running_state) + __field(u32, psci_state) + __field(u8, affinity) + ), + + TP_fast_assign( + if (proc->validation_bits & CPER_ARM_VALID_AFFINITY_LEVEL) + __entry->affinity = proc->affinity_level; + else + __entry->affinity = ~0; + if (proc->validation_bits & CPER_ARM_VALID_MPIDR) + __entry->mpidr = proc->mpidr; + else + __entry->mpidr = 0ULL; + __entry->midr = proc->midr; + if (proc->validation_bits & CPER_ARM_VALID_RUNNING_STATE) { + __entry->running_state = proc->running_state; + __entry->psci_state = proc->psci_state; + } else { + __entry->running_state = ~0; + __entry->psci_state = ~0; + } + ), + + TP_printk("affinity level: %d; MPIDR: %016llx; MIDR: %016llx; " + "running state: %d; PSCI state: %d", + __entry->affinity, __entry->mpidr, __entry->midr, + __entry->running_state, __entry->psci_state) +); + +/* * Non-Standard Section Report * * This event is generated when hardware detected a hardware