From patchwork Mon May 8 21:23:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Mason X-Patchwork-Id: 9716733 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 71CF060365 for ; Mon, 8 May 2017 21:24:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6342B24B5B for ; Mon, 8 May 2017 21:24:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 57B3F269DA; Mon, 8 May 2017 21:24:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DDC1024B5B for ; Mon, 8 May 2017 21:24:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756876AbdEHVYF (ORCPT ); Mon, 8 May 2017 17:24:05 -0400 Received: from mail-pf0-f178.google.com ([209.85.192.178]:34582 "EHLO mail-pf0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752921AbdEHVYE (ORCPT ); Mon, 8 May 2017 17:24:04 -0400 Received: by mail-pf0-f178.google.com with SMTP id e64so38939303pfd.1 for ; Mon, 08 May 2017 14:24:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=UF3NzG3cWDiV+O0cEVHSG0cVtFUnCSHY1g9nUbeiFeg=; b=RCmp0vZZCffNAM9ikOLSsrUHR1vGwvL97eTDvzyVeaq6EYpGR+WdNjqMTqvxiSV7j2 slXKF+pBXffjzckZ+DtKIIY7mUI32Epa+rWxiwnHsrKXgSdLcYWr00qDUxTa8RROaP2e 2knqli1xcjKs4hruZEySNElwMeqIoTvekmuyA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=UF3NzG3cWDiV+O0cEVHSG0cVtFUnCSHY1g9nUbeiFeg=; b=TXFyb8MpzoGDag17wCI2EmBTI9HFSKamvBuhbNhl+FaY82iznW+KJEbxGverkjLIDV oBNrj/TYeuEYioE9hrhJMr84lKyCor3i+V4RqFOAti5dq6q6JIxRMVFT2UcPEVvQdZ/U c9rEb2OMLEMACRaxbZL7m8w59X6l3bJduKn9ZmYv7b8hkIMWZ3UWM0FAfkyz2PS0BmzT ydPt691Q3eXCI1+tM13xxYD/htPuHIMfUFayEJkT6jTJflJ2NFo+EIlQfeq/gisbqnLd DprSAiqOZMry/ZO5y3aKWW0lKKXcrZGeQH9HBKOX+H5/UqD3o5MxueigwdJI6SDHwrky FwFA== X-Gm-Message-State: AN3rC/7dCRh/nk7BH2H7cP40DOGh0RplwDGmqOp4nWdBNPICnv60UocX aNW70W2ai+mY96hd X-Received: by 10.99.44.82 with SMTP id s79mr20869664pgs.219.1494278643714; Mon, 08 May 2017 14:24:03 -0700 (PDT) Received: from broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id o74sm27537877pfa.14.2017.05.08.14.23.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 08 May 2017 14:24:03 -0700 (PDT) Date: Mon, 8 May 2017 17:23:48 -0400 From: Jon Mason To: Loc Ho Cc: Jon Masters , Rafael Wysocki , Len Brown , Robert Moore , Lv Zheng , linux-acpi@vger.kernel.org, Linux Kernel Mailing List , devel@acpica.org, BCM Kernel Feedback Subject: Re: [PATCH] ACPI: SPCR: Use access width to determine mmio usage Message-ID: <20170508212347.GA3601@broadcom.com> References: <1493910330-17913-1-git-send-email-jon.mason@broadcom.com> <4e11bb2b-7cec-6a7b-ca2b-88be31a98b7d@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Mon, May 08, 2017 at 01:51:20PM -0700, Loc Ho wrote: > Hi Jon, > > On Mon, May 8, 2017 at 1:34 PM, Jon Mason wrote: > > On Mon, May 8, 2017 at 3:57 PM, Loc Ho wrote: > >> Hi Jon, > >> > >>>> > >>>>>> The current SPCR code does not check the access width of the mmio, and > >>>>>> uses a default of 8bit register accesses. This prevents devices that > >>>>>> only do 16 or 32bit register accesses from working. By simply checking > >>>>>> this field and setting the mmio string appropriately, this issue can be > >>>>>> corrected. To prevent any legacy issues, the code will default to 8bit > >>>>>> accesses if the value is anything but 16 or 32. > >>>>> > >>>>> Thanks for this. Just as an FYI I've a running discussion with Microsoft > >>>>> about defining additional UART subtypes in the DBG2 for special case > >>>>> UARTs. Specifically, I want to address AppliedMicro's special 8250 dw IP > >>>>> that also has a non-standard clock. At this time, there is general > >>>>> agreement to use the access width for some cases rather than defining > >>>>> yet more subtypes - so your patch is good. > >>>>> > >>>>> Loc/Applied: please track this thread, incorporate feedback, and also > >>>>> track the other general recent discussions of 8250 dw from this week. > >>>> > >>>> Thanks for forward me this patch. This patch does not work with X-Gene > >>>> v1 and v2 SoC's. As BIOS SPCR encodes these info as: > >>>> > >>>> Bit Width: 32 > >>>> Bit Offset: 0 > >>>> Encoded Access Width: 01 (Byte Access) > >>>> > >>>> With this patch, it would use the "mmio" instead the "mmio32" as with > >>>> this patch - https://patchwork.kernel.org/patch/9460959 > >>> > >>> I think this is why we need the DBG2 subtype for Applied X-Gene1. I'm > >>> hoping the update to the SPCR/DBG2 spec is done soon. > >> > >> We can't rely on the BIOS change to support this new subtype as we > >> have system that is already in production deployment. When these > >> system upgrade to new version of the OS (stock, RHELSA, or whatever), > >> they will break. We need the patch from > >> https://patchwork.kernel.org/patch/9460959/ rolled upstream. > > > > There is no reason why the patch you reference cannot co-exist with > > the one I am submitting here. In this case, my patch would set it to > > mmio, then the patch you link above would reset it to mmio32. > > Personally, I would recommend a big, fat comment on why this extra > > step is necessary, but it should work as desired. Alternatively, we > > could add some kind of quirk library (similar to > > qdf2400_erratum_44_present) where the OEM/OEM Table ID is referenced > > and workaround applied. Thoughts? > > That's was my first version but after seeing both versions, I think > they are better solution as it works for more SoC's than just our. As > you had suggested, we should apply your patch and > https://patchwork.kernel.org/patch/9460959. The third patch - > https://patchwork.kernel.org/patch/9462183/ - conflicts with your. > > Summary: > 1. Applied your - https://lkml.org/lkml/2017/5/4/450 > 2. Applied this one - https://patchwork.kernel.org/patch/9460959/ > > -Loc What if we simply applied the following (100% untested) patch to add the quirk framework I was suggesting? It can be applied on top of the patch I submitted previously. --- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/acpi/spcr.c b/drivers/acpi/spcr.c index 63b690d142f1..c87569b345e3 100644 --- a/drivers/acpi/spcr.c +++ b/drivers/acpi/spcr.c @@ -36,6 +36,14 @@ static bool qdf2400_erratum_44_present(struct acpi_table_header *h) return false; } +static void spcr_quirks(struct acpi_table_spcr *table, char **iotype) +{ + struct acpi_table_header *h = &table->header; + + if (!memcmp(h->oem_table_id, "XGENESPC", ACPI_OEM_TABLE_ID_SIZE)) + *iotype = "mmio32"; +} + /** * parse_spcr() - parse ACPI SPCR table and add preferred console * @@ -88,6 +96,9 @@ int __init parse_spcr(bool earlycon) iotype = "mmio32"; break; } + + /* Fixup any non-standard compliant devices */ + spcr_quirks(table, &iotype); } else iotype = "io";