| Message ID | 20230905184406.135851-2-Benjamin.Cheatham@amd.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere, archived |
| Headers | show |
| Series | CXL, ACPI, APEI, EINJ: Update EINJ for CXL 1.1 error types | expand |
Hi Ben, kernel test robot noticed the following build warnings: [auto build test WARNING on rafael-pm/linux-next] [also build test WARNING on linus/master v6.5 next-20230905] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Ben-Cheatham/CXL-PCIE-Add-cxl_rcrb_addr-file-to-dport_dev/20230906-025405 base: https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git linux-next patch link: https://lore.kernel.org/r/20230905184406.135851-2-Benjamin.Cheatham%40amd.com patch subject: [PATCH v3 1/3] CXL, PCIE: Add cxl_rcrb_addr file to dport_dev config: parisc-allyesconfig (https://download.01.org/0day-ci/archive/20230906/202309060435.NqPCZpql-lkp@intel.com/config) compiler: hppa-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230906/202309060435.NqPCZpql-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202309060435.NqPCZpql-lkp@intel.com/ All warnings (new ones prefixed by >>): drivers/cxl/core/port.c: In function 'cxl_rcrb_addr_show': >> drivers/cxl/core/port.c:953:38: warning: format '%llx' expects argument of type 'long long unsigned int', but argument 3 has type 'resource_size_t' {aka 'unsigned int'} [-Wformat=] 953 | return sysfs_emit(buf, "0x%llx\n", dport->rcrb.base); | ~~~^ ~~~~~~~~~~~~~~~~ | | | | | resource_size_t {aka unsigned int} | long long unsigned int | %x vim +953 drivers/cxl/core/port.c 940 941 static ssize_t cxl_rcrb_addr_show(struct device *dev, 942 struct device_attribute *attr, char *buf) 943 { 944 struct cxl_dport *dport; 945 946 if (!cxl_root) 947 return -ENODEV; 948 949 dport = cxl_find_dport_by_dev(cxl_root, dev); 950 if (!dport) 951 return -ENODEV; 952 > 953 return sysfs_emit(buf, "0x%llx\n", dport->rcrb.base); 954 } 955 DEVICE_ATTR_RO(cxl_rcrb_addr); 956
diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index 087f762ebfd5..a7d169235543 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -177,6 +177,14 @@ Description: integer reflects the hardware port unique-id used in the hardware decoder target list. +What: /sys/bus/cxl/devices/portX/dportY/cxl_rcrb_addr +Date: August, 2023 +KernelVersion: v6.6 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) The 'cxl_rcrb_addr' device file gives the MMIO base address + of the RCRB of the corresponding CXL 1.1 downstream port. Only + present for CXL 1.1 dports. What: /sys/bus/cxl/devices/decoderX.Y Date: June, 2021 diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index d1c559879dcc..3e2ca946bf47 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -676,6 +676,8 @@ static int cxl_acpi_probe(struct platform_device *pdev) if (IS_ERR(root_port)) return PTR_ERR(root_port); + set_cxl_root(root_port); + rc = bus_for_each_dev(adev->dev.bus, NULL, root_port, add_host_bridge_dport); if (rc < 0) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 724be8448eb4..b69fd1c1d5d6 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -875,6 +875,14 @@ struct cxl_port *find_cxl_root(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(find_cxl_root, CXL); +static struct cxl_port *cxl_root; + +void set_cxl_root(struct cxl_port *root_port) +{ + cxl_root = root_port; +} +EXPORT_SYMBOL_NS_GPL(set_cxl_root, CXL); + static struct cxl_dport *find_dport(struct cxl_port *port, int id) { struct cxl_dport *dport; @@ -930,11 +938,30 @@ static void cond_cxl_root_unlock(struct cxl_port *port) device_unlock(&port->dev); } +static ssize_t cxl_rcrb_addr_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cxl_dport *dport; + + if (!cxl_root) + return -ENODEV; + + dport = cxl_find_dport_by_dev(cxl_root, dev); + if (!dport) + return -ENODEV; + + return sysfs_emit(buf, "0x%llx\n", dport->rcrb.base); +} +DEVICE_ATTR_RO(cxl_rcrb_addr); + static void cxl_dport_remove(void *data) { struct cxl_dport *dport = data; struct cxl_port *port = dport->port; + if (dport->rch) + device_remove_file(dport->dport_dev, &dev_attr_cxl_rcrb_addr); + xa_erase(&port->dports, (unsigned long) dport->dport_dev); put_device(dport->dport_dev); } @@ -1021,6 +1048,12 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, if (rc) return ERR_PTR(rc); + if (dport->rch && dport->rcrb.base != CXL_RESOURCE_NONE) { + rc = device_create_file(dport_dev, &dev_attr_cxl_rcrb_addr); + if (rc) + return ERR_PTR(rc); + } + return dport; } diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 76d92561af29..4d5bce4bae7e 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -690,6 +690,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host, resource_size_t component_reg_phys, struct cxl_dport *parent_dport); struct cxl_port *find_cxl_root(struct cxl_port *port); +void set_cxl_root(struct cxl_port *root_port); + int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); void cxl_bus_rescan(void); void cxl_bus_drain(void);
Add cxl_rcrb_addr to the dport_dev (normally represented by a pcie device) for CXL RCH root ports. The file will print the RCRB base MMIO address of the root port when read and will be used by users looking to inject CXL EINJ error types for RCH hosts. Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com> --- Documentation/ABI/testing/sysfs-bus-cxl | 8 ++++++ drivers/cxl/acpi.c | 2 ++ drivers/cxl/core/port.c | 33 +++++++++++++++++++++++++ drivers/cxl/cxl.h | 2 ++ 4 files changed, 45 insertions(+)