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AJvYcCWJK3KpA5Df9ADUbtM+cflYmfyBgk/OcsxnWXZ9Gs+GxUhXmu+o7JRRqISIxjjxk1Y8dfxxLMaWTPsFmVV6WVwRVfU12S+SXFn+Lg== X-Gm-Message-State: AOJu0YwragcuOsTBHNUnh4iANw75909x9qhuSp4Qwa2s/6R3lBD0UM+4 CeQ4mFjQRMey82dWA/yC1y/WVxgRM78WmoZqfvTuj3oGtdIOf27hgTa+jjTa624= X-Google-Smtp-Source: AGHT+IFyXVXcwEnHkFr+M+B09gwoggwiZPCR+TNh4urQv2uHfL8+aZj9PiLWU/sney1s+CzXzICoGA== X-Received: by 2002:a05:6a20:6597:b0:1bc:a4c5:445b with SMTP id adf61e73a8af0-1bca4c54494mr873421637.24.1718630079903; Mon, 17 Jun 2024 06:14:39 -0700 (PDT) Received: from L6YN4KR4K9.bytedance.net ([139.177.225.245]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855f0260csm78801785ad.200.2024.06.17.06.14.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 17 Jun 2024 06:14:39 -0700 (PDT) From: Yunhui Cui To: rafael@kernel.org, lenb@kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, sunilvl@ventanamicro.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, bhelgaas@google.com, james.morse@arm.com, jeremy.linton@arm.com, Jonathan.Cameron@huawei.com, pierre.gondois@arm.com, sudeep.holla@arm.com, tiantao6@huawei.com Cc: Yunhui Cui , Conor Dooley Subject: [PATCH v6 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT Date: Mon, 17 Jun 2024 21:14:24 +0800 Message-Id: <20240617131425.7526-2-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20240617131425.7526-1-cuiyunhui@bytedance.com> References: <20240617131425.7526-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Before cacheinfo can be built correctly, we need to initialize level and type. Since RISC-V currently does not have a register group that describes cache-related attributes like ARM64, we cannot obtain them directly, so now we obtain cache leaves from the ACPI PPTT table (acpi_get_cache_info()) and set the cache type through split_levels. Suggested-by: Jeremy Linton Suggested-by: Sudeep Holla Reviewed-by: Conor Dooley Reviewed-by: Sunil V L Reviewed-by: Jeremy Linton Reviewed-by: Sudeep Holla Signed-off-by: Yunhui Cui --- arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c index 30a6878287ad..d6c108c50cba 100644 --- a/arch/riscv/kernel/cacheinfo.c +++ b/arch/riscv/kernel/cacheinfo.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #include #include @@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu) struct device_node *prev = NULL; int levels = 1, level = 1; + if (!acpi_disabled) { + int ret, fw_levels, split_levels; + + ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels); + if (ret) + return ret; + + BUG_ON((split_levels > fw_levels) || + (split_levels + fw_levels > this_cpu_ci->num_leaves)); + + for (; level <= this_cpu_ci->num_levels; level++) { + if (level <= split_levels) { + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); + } else { + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); + } + } + return 0; + } + if (of_property_read_bool(np, "cache-size")) ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); if (of_property_read_bool(np, "i-cache-size"))