| Message ID | 20241112221335.432583-2-dave.jiang@intel.com (mailing list archive) |
|---|---|
| State | RFC, archived |
| Headers | show |
| Series | acpi/hmat / cxl: Add exclusive caching enumeration and RAS support | expand |
On Tue, 12 Nov 2024 15:12:33 -0700 Dave Jiang <dave.jiang@intel.com> wrote: > Store the address mode as part of the cache attriutes. Export the mode > attribute to sysfs as all other cache attributes. > > Link: https://lore.kernel.org/linux-cxl/668333b17e4b2_5639294fd@dwillia2-xfh.jf.intel.com.notmuch/ > Signed-off-by: Dave Jiang <dave.jiang@intel.com> One trivial suggestion that I don't care that much about. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > v2: > - Fix spelling errors (Jonathan) > - Change UNKNOWN to RESERVED (Jonathan) > --- > Documentation/ABI/stable/sysfs-devices-node | 6 ++++++ > drivers/acpi/numa/hmat.c | 3 +++ > drivers/base/node.c | 2 ++ > include/linux/node.h | 7 +++++++ > 4 files changed, 18 insertions(+) > > diff --git a/Documentation/ABI/stable/sysfs-devices-node b/Documentation/ABI/stable/sysfs-devices-node > index 402af4b2b905..725ef0e1e01f 100644 > --- a/Documentation/ABI/stable/sysfs-devices-node > +++ b/Documentation/ABI/stable/sysfs-devices-node > @@ -177,6 +177,12 @@ Description: > The cache write policy: 0 for write-back, 1 for write-through, > other or unknown. > > +What: /sys/devices/system/node/nodeX/memory_side_cache/indexY/mode Mode feels perhaps a bit to vague. Maybe address_mode? > +Date: September 2024 > +Contact: Dave Jiang <dave.jiang@intel.com> > +Description: > + The address mode: 0 for reserved, 1 for extended-linear. > + > What: /sys/devices/system/node/nodeX/x86/sgx_total_bytes > Date: November 2021 > Contact: Jarkko Sakkinen <jarkko@kernel.org> > diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c > index 1a902a02390f..39524f36be5b 100644 > --- a/drivers/acpi/numa/hmat.c > +++ b/drivers/acpi/numa/hmat.c > @@ -506,6 +506,9 @@ static __init int hmat_parse_cache(union acpi_subtable_headers *header, > switch ((attrs & ACPI_HMAT_CACHE_ASSOCIATIVITY) >> 8) { > case ACPI_HMAT_CA_DIRECT_MAPPED: > tcache->cache_attrs.indexing = NODE_CACHE_DIRECT_MAP; > + /* Extended Linear mode is only valid if cache is direct mapped */ > + if (cache->address_mode == ACPI_HMAT_CACHE_MODE_EXTENDED_LINEAR) > + tcache->cache_attrs.mode = NODE_CACHE_MODE_EXTENDED_LINEAR; > break; > case ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING: > tcache->cache_attrs.indexing = NODE_CACHE_INDEXED;
diff --git a/Documentation/ABI/stable/sysfs-devices-node b/Documentation/ABI/stable/sysfs-devices-node index 402af4b2b905..725ef0e1e01f 100644 --- a/Documentation/ABI/stable/sysfs-devices-node +++ b/Documentation/ABI/stable/sysfs-devices-node @@ -177,6 +177,12 @@ Description: The cache write policy: 0 for write-back, 1 for write-through, other or unknown. +What: /sys/devices/system/node/nodeX/memory_side_cache/indexY/mode +Date: September 2024 +Contact: Dave Jiang <dave.jiang@intel.com> +Description: + The address mode: 0 for reserved, 1 for extended-linear. + What: /sys/devices/system/node/nodeX/x86/sgx_total_bytes Date: November 2021 Contact: Jarkko Sakkinen <jarkko@kernel.org> diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c index 1a902a02390f..39524f36be5b 100644 --- a/drivers/acpi/numa/hmat.c +++ b/drivers/acpi/numa/hmat.c @@ -506,6 +506,9 @@ static __init int hmat_parse_cache(union acpi_subtable_headers *header, switch ((attrs & ACPI_HMAT_CACHE_ASSOCIATIVITY) >> 8) { case ACPI_HMAT_CA_DIRECT_MAPPED: tcache->cache_attrs.indexing = NODE_CACHE_DIRECT_MAP; + /* Extended Linear mode is only valid if cache is direct mapped */ + if (cache->address_mode == ACPI_HMAT_CACHE_MODE_EXTENDED_LINEAR) + tcache->cache_attrs.mode = NODE_CACHE_MODE_EXTENDED_LINEAR; break; case ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING: tcache->cache_attrs.indexing = NODE_CACHE_INDEXED; diff --git a/drivers/base/node.c b/drivers/base/node.c index eb72580288e6..744be5470728 100644 --- a/drivers/base/node.c +++ b/drivers/base/node.c @@ -244,12 +244,14 @@ CACHE_ATTR(size, "%llu") CACHE_ATTR(line_size, "%u") CACHE_ATTR(indexing, "%u") CACHE_ATTR(write_policy, "%u") +CACHE_ATTR(mode, "%u") static struct attribute *cache_attrs[] = { &dev_attr_indexing.attr, &dev_attr_size.attr, &dev_attr_line_size.attr, &dev_attr_write_policy.attr, + &dev_attr_mode.attr, NULL, }; ATTRIBUTE_GROUPS(cache); diff --git a/include/linux/node.h b/include/linux/node.h index 9a881c2208b3..fdecb760ef49 100644 --- a/include/linux/node.h +++ b/include/linux/node.h @@ -57,6 +57,11 @@ enum cache_write_policy { NODE_CACHE_WRITE_OTHER, }; +enum cache_mode { + NODE_CACHE_MODE_RESERVED, + NODE_CACHE_MODE_EXTENDED_LINEAR, +}; + /** * struct node_cache_attrs - system memory caching attributes * @@ -65,6 +70,7 @@ enum cache_write_policy { * @size: Total size of cache in bytes * @line_size: Number of bytes fetched on a cache miss * @level: The cache hierarchy level + * @mode: The address mode */ struct node_cache_attrs { enum cache_indexing indexing; @@ -72,6 +78,7 @@ struct node_cache_attrs { u64 size; u16 line_size; u8 level; + u16 mode; }; #ifdef CONFIG_HMEM_REPORTING
Store the address mode as part of the cache attriutes. Export the mode attribute to sysfs as all other cache attributes. Link: https://lore.kernel.org/linux-cxl/668333b17e4b2_5639294fd@dwillia2-xfh.jf.intel.com.notmuch/ Signed-off-by: Dave Jiang <dave.jiang@intel.com> --- v2: - Fix spelling errors (Jonathan) - Change UNKNOWN to RESERVED (Jonathan) --- Documentation/ABI/stable/sysfs-devices-node | 6 ++++++ drivers/acpi/numa/hmat.c | 3 +++ drivers/base/node.c | 2 ++ include/linux/node.h | 7 +++++++ 4 files changed, 18 insertions(+)