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[GIT,PULL] Compute Express Link (CXL) for 6.2

Message ID 6395383a608a5_4962d294e9@dwillia2-mobl3.amr.corp.intel.com.notmuch (mailing list archive)
State Mainlined, archived
Headers show
Series [GIT,PULL] Compute Express Link (CXL) for 6.2 | expand

Pull-request

git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl tags/cxl-for-6.2

Message

Dan Williams Dec. 11, 2022, 1:54 a.m. UTC 
Hi Linus, please pull from:

  git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl tags/cxl-for-6.2

...to receive the CXL update for v6.2.

While it may seem backwards, the CXL update this time around includes
some focus on CXL 1.x enabling where the work to date had been with CXL
2.0 (VH topologies) in mind.  First generation CXL can mostly be
supported via BIOS, similar to DDR, however it became clear there are
use cases for OS native CXL error handling and some CXL 3.0 endpoint
features can be deployed on CXL 1.x hosts (Restricted CXL Host (RCH)
topologies). So, this update brings RCH topologies into the Linux CXL
device model.

In support of the ongoing CXL 2.0+ enabling 2 new core kernel
facilities are added. One is the ability for the kernel to flag
collisions between userspace access to PCI configuration registers and
kernel accesses. This is brought on by the PCIe Data-Object-Exchange
(DOE) facility, a hardware mailbox over config-cycles. The other is a
cpu_cache_invalidate_memregion() API that maps to wbinvd_on_all_cpus()
on x86. To prevent abuse it is disabled in guest VMs and architectures
that do not support it yet. The CXL paths that need it, dynamic memory
region creation and security commands (erase / unlock), are disabled
when it is not present.

As for the CXL 2.0+ this cycle the subsystem gains support Persistent
Memory Security commands, error handling in response to PCIe AER
notifications, and support for the "XOR" host bridge interleave
algorithm.

That last feature, "XOR" interleave support, is built on top of the
ACPICA update for this cycle [1]. The shortlog and diffstat below are
from a test merge with the pending ACPI updates. So either pull the ACPI
tree first, or understand you will get some unrelated ACPICA updates in
this pull.

This has all appeared in -next with no known outstanding issues. The
x86, ACPI, and PCI touches have acks from their respective maintainers.

[1]: f350c68e3cd5 ("ACPICA: Add CXL 3.0 structures (CXIMS & RDPAS) to the CEDT table")

---

The following changes since commit f0c4d9fc9cc9462659728d168387191387e903cc:

  Linux 6.1-rc4 (2022-11-06 15:07:11 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl tags/cxl-for-6.2

for you to fetch changes up to f04facfb993de47e2133b2b842d72b97b1c50162:

  cxl/region: Fix memdev reuse check (2022-12-08 13:03:47 -0800)

----------------------------------------------------------------
cxl for 6.2

- Add the cpu_cache_invalidate_memregion() API for cache flushing in
  response to physical memory reconfiguration, or memory-side data
  invalidation from operations like secure erase or memory-device unlock.

- Add a facility for the kernel to warn about collisions between kernel
  and userspace access to PCI configuration registers

- Add support for Restricted CXL Host (RCH) topologies (formerly CXL 1.1)

- Add handling and reporting of CXL errors reported via the PCIe AER
  mechanism

- Add support for CXL Persistent Memory Security commands

- Add support for the "XOR" algorithm for CXL host bridge interleave

- Rework / simplify CXL to NVDIMM interactions

- Miscellaneous cleanups and fixes

----------------------------------------------------------------

Adam Manzanares (1):
      cxl: Replace HDM decoder granularity magic numbers

Alison Schofield (3):
      cxl/acpi: Support CXL XOR Interleave Math (CXIMS)
      tools/testing/cxl: Add XOR Math support to cxl_test
      cxl/acpi: Fail decoder add if CXIMS for HBIG is missing

Colin Ian King (1):
      cxl/region: Fix spelling mistake "memergion" -> "memregion"

Dan Williams (34):
      tools/testing/cxl: Add bridge mocking support
      cxl/acpi: Simplify cxl_nvdimm_bridge probing
      cxl/region: Drop redundant pmem region release handling
      cxl/pmem: Refactor nvdimm device registration, delete the workqueue
      cxl/pmem: Remove the cxl_pmem_wq and related infrastructure
      cxl/acpi: Move rescan to the workqueue
      tools/testing/cxl: Make mock CEDT parsing more robust
      cxl/region: Fix missing probe failure
      cxl/pmem: Enforce keyctl ABI for PMEM security
      nvdimm/region: Move cache management to the region driver
      cxl/region: Manage CPU caches relative to DPA invalidation events
      cxl/pci: Cleanup repeated code in cxl_probe_regs() helpers
      cxl/pci: Cleanup cxl_map_device_regs()
      cxl/pci: Kill cxl_map_regs()
      cxl/core/regs: Make cxl_map_{component, device}_regs() device generic
      cxl/port: Limit the port driver to just the HDM Decoder Capability
      cxl/pci: Prepare for mapping RAS Capability Structure
      cxl/pci: Find and map the RAS Capability Structure
      cxl/pci: Add (hopeful) error handling support
      Merge "ACPICA: Add CXL 3.0 structures..." into for-6.2/cxl-xor
      cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_mem
      cxl/port: Add RCD endpoint port enumeration
      tools/testing/cxl: Add an RCH topology
      Merge branch 'for-6.2/cxl-security' into for-6.2/cxl
      Merge branch 'for-6.2/cxl-aer' into for-6.2/cxl
      Merge branch 'for-6.2/cxl-xor' into for-6.2/cxl
      cxl/regs: Fix sparse warning
      tools/testing/cxl: Require cache invalidation bypass
      cxl/security: Fix Get Security State output payload endian handling
      cxl/mbox: Enable cxl_mbox_send_cmd() users to validate output size
      cxl/mbox: Add variable output size validation for internal commands
      cxl/security: Drop security command ioctl uapi
      cxl/pci: Add some type-safety to the AER trace points
      cxl/pci: Remove endian confusion

Dave Jiang (23):
      cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation
      tools/testing/cxl: Add "Get Security State" opcode support
      cxl/pmem: Add "Set Passphrase" security command support
      tools/testing/cxl: Add "Set Passphrase" opcode support
      cxl/pmem: Add Disable Passphrase security command support
      tools/testing/cxl: Add "Disable" security opcode support
      cxl/pmem: Add "Freeze Security State" security command support
      tools/testing/cxl: Add "Freeze Security State" security opcode support
      cxl/pmem: Add "Unlock" security command support
      tools/testing/cxl: Add "Unlock" security opcode support
      cxl/pmem: Add "Passphrase Secure Erase" security command support
      tools/testing/cxl: Add "passphrase secure erase" opcode support
      nvdimm/cxl/pmem: Add support for master passphrase disable security command
      cxl/pmem: add id attribute to CXL based nvdimm
      tools/testing/cxl: add mechanism to lock mem device for testing
      cxl/pmem: add provider name to cxl pmem dimm attribute group
      libnvdimm: Introduce CONFIG_NVDIMM_SECURITY_TEST flag
      cxl: add dimm_id support for __nvdimm_create()
      cxl/pci: add tracepoint events for CXL RAS
      PCI/AER: Add optional logging callback for correctable error
      cxl/pci: Add callback to log AER correctable error
      cxl: update names for interleave granularity conversion macros
      cxl: update names for interleave ways conversion macros

Davidlohr Bueso (1):
      memregion: Add cpu_cache_invalidate_memregion() interface

Fan Ni (1):
      cxl/region: Fix memdev reuse check

Ira Weiny (2):
      PCI: Allow drivers to request exclusive config regions
      cxl/doe: Request exclusive DOE access

Robert Richter (8):
      cxl/core: Remove duplicate declaration of devm_cxl_iomap_block()
      cxl/core: Check physical address before mapping it in devm_cxl_iomap_block()
      cxl: Unify debug messages when calling devm_cxl_add_port()
      cxl: Unify debug messages when calling devm_cxl_add_dport()
      cxl/acpi: Improve debug messages in cxl_acpi_probe()
      cxl/ACPI: Register CXL host ports by bridge device
      cxl/acpi: Extract component registers of restricted hosts from RCRB
      cxl/acpi: Warn about an invalid CHBCR in an existing CHBS entry

Terry Bowman (1):
      cxl/acpi: Set ACPI's CXL _OSC to indicate RCD mode support

 Documentation/ABI/testing/sysfs-bus-nvdimm |  14 +
 Documentation/PCI/pci-error-recovery.rst   |   7 +
 arch/x86/Kconfig                           |   1 +
 arch/x86/mm/pat/set_memory.c               |  18 ++
 drivers/acpi/nfit/intel.c                  |  30 +-
 drivers/acpi/pci_root.c                    |   1 +
 drivers/cxl/Kconfig                        |  18 ++
 drivers/cxl/Makefile                       |   2 +-
 drivers/cxl/acpi.c                         | 275 ++++++++++++++---
 drivers/cxl/core/core.h                    |   8 -
 drivers/cxl/core/hdm.c                     |  45 +--
 drivers/cxl/core/mbox.c                    | 102 ++++---
 drivers/cxl/core/memdev.c                  |   1 +
 drivers/cxl/core/pci.c                     |   5 +-
 drivers/cxl/core/pmem.c                    | 109 ++++---
 drivers/cxl/core/port.c                    | 216 +++++++++-----
 drivers/cxl/core/region.c                  | 112 ++++++-
 drivers/cxl/core/regs.c                    | 242 ++++++++++-----
 drivers/cxl/cxl.h                          | 140 +++++----
 drivers/cxl/cxlmem.h                       |  64 +++-
 drivers/cxl/cxlpci.h                       |   9 -
 drivers/cxl/mem.c                          |  74 ++++-
 drivers/cxl/pci.c                          | 228 ++++++++++++---
 drivers/cxl/pmem.c                         | 407 ++++++--------------------
 drivers/cxl/security.c                     | 202 +++++++++++++
 drivers/nvdimm/Kconfig                     |  12 +
 drivers/nvdimm/dimm_devs.c                 |   9 +-
 drivers/nvdimm/region.c                    |  11 +
 drivers/nvdimm/region_devs.c               |  50 +++-
 drivers/nvdimm/security.c                  |  43 ++-
 drivers/pci/pci-sysfs.c                    |   7 +
 drivers/pci/pcie/aer.c                     |   8 +-
 drivers/pci/probe.c                        |   6 +
 include/linux/ioport.h                     |   2 +
 include/linux/libnvdimm.h                  |   7 +
 include/linux/memregion.h                  |  38 +++
 include/linux/pci.h                        |  20 ++
 include/trace/events/cxl.h                 | 112 +++++++
 include/uapi/linux/pci_regs.h              |   1 +
 kernel/resource.c                          |  13 +-
 lib/Kconfig                                |   3 +
 tools/testing/cxl/Kbuild                   |   2 +
 tools/testing/cxl/config_check.c           |   2 +
 tools/testing/cxl/test/cxl.c               | 303 +++++++++++++++++--
 tools/testing/cxl/test/mem.c               | 453 ++++++++++++++++++++++++++++-
 tools/testing/cxl/test/mock.c              |  19 ++
 tools/testing/cxl/test/mock.h              |   3 +
 tools/testing/nvdimm/Kbuild                |   1 -
 tools/testing/nvdimm/dimm_devs.c           |  30 --
 49 files changed, 2649 insertions(+), 836 deletions(-)
 create mode 100644 drivers/cxl/security.c
 create mode 100644 include/trace/events/cxl.h
 delete mode 100644 tools/testing/nvdimm/dimm_devs.c

Comments

pr-tracker-bot@kernel.org Dec. 12, 2022, 10:46 p.m. UTC | #1 
The pull request you sent on Sat, 10 Dec 2022 17:54:02 -0800:

> git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl tags/cxl-for-6.2

has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/c1f0fcd85d3d66f002fc1a4986363840fcca766d

Thank you!