From patchwork Sat Aug 6 11:42:36 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lutomirski X-Patchwork-Id: 1041522 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p76BhIV2025779 for ; Sat, 6 Aug 2011 11:43:18 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754249Ab1HFLnH (ORCPT ); Sat, 6 Aug 2011 07:43:07 -0400 Received: from DMZ-MAILSEC-SCANNER-2.MIT.EDU ([18.9.25.13]:45900 "EHLO dmz-mailsec-scanner-2.mit.edu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753930Ab1HFLnD (ORCPT ); Sat, 6 Aug 2011 07:43:03 -0400 X-AuditID: 1209190d-b7be0ae000000a16-7b-4e3d28237860 Received: from mailhub-auth-4.mit.edu ( [18.7.62.39]) by dmz-mailsec-scanner-2.mit.edu (Symantec Messaging Gateway) with SMTP id BB.72.02582.3282D3E4; Sat, 6 Aug 2011 07:40:19 -0400 (EDT) Received: from outgoing.mit.edu (OUTGOING-AUTH.MIT.EDU [18.7.22.103]) by mailhub-auth-4.mit.edu (8.13.8/8.9.2) with ESMTP id p76Bh1Ht030297; Sat, 6 Aug 2011 07:43:01 -0400 Received: from localhost (207-172-69-77.c3-0.smr-ubr3.sbo-smr.ma.static.cable.rcn.com [207.172.69.77]) (authenticated bits=0) (User authenticated as luto@ATHENA.MIT.EDU) by outgoing.mit.edu (8.13.6/8.12.4) with ESMTP id p76Bgxrq024595 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES128-SHA bits=128 verify=NOT); Sat, 6 Aug 2011 07:43:00 -0400 (EDT) From: Andy Lutomirski To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: Fenghua Yu , Matthew Garrett , Len Brown , linux-acpi@vger.kernel.org, Ingo Molnar , Andy Lutomirski Subject: [PATCH v2 2/2] x86: Enable monitor/mwait on Intel if BIOS hasn't already Date: Sat, 6 Aug 2011 07:42:36 -0400 Message-Id: <67feadbc353e826cf5d715d06f8ff1f92277a97d.1312630712.git.luto@mit.edu> X-Mailer: git-send-email 1.7.6 In-Reply-To: References: In-Reply-To: References: X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBIsWRmVeSWpSXmKPExsUixG6nrqusYetn8PKLpEXflaPsFm3THC12 PnzLZrF8Xz+jxeVdc9gstlxqZrW4+nA2i8WPDY9ZHTg8brX9YfbYOesuu8fiPS+ZPDat6mTz WHfjK7vH501yAWxRXDYpqTmZZalF+nYJXBkvl3kVbOKp6Hizg7GB8QVnFyMnh4SAicSWPXcY IWwxiQv31rN1MXJxCAnsY5R49f8HM4SznlHi/fy5LCBVQgJPmSTmfwOz2QRUJDqWPmACsUUE DCS2rHzBCtLALHCFUeLi/BvMIAlhgUCJnu2NrCA2i4CqxPKm62A2r0CQxKXri1ghVstJHLn8 HGwQJ9Cgz1/b2SCW6UscOTqVDZf4BEaBBYwMqxhlU3KrdHMTM3OKU5N1i5MT8/JSi3SN9HIz S/RSU0o3MYICmFOSdwfju4NKhxgFOBiVeHgfytj4CbEmlhVX5h5ilORgUhLlZVW39RPiS8pP qcxILM6ILyrNSS0+xCjBwawkwpujC1TOm5JYWZValA+TkuZgURLnVfP+7yskkJ5YkpqdmlqQ WgSTleHgUJLgZQJGqpBgUWp6akVaZk4JQpqJgxNkOA/QcDuQxbzFBYm5xZnpEPlTjIpS4ryS IM0CIImM0jy4XliCecUoDvSKMO9XkHYeYHKC634FNJgJaHDuE5Cri0sSEVJSDYxSjD8ZP+pk /imMv63o3Wj38cunHfFh7H8XzzNzu8PALaLHyRxqslT4b7FYg4dex/NLzE+Sci47z/sxL/pO SMsPDp2tjtsfqSyJKswpdJWpXG+6IOHIIQ+bc8Js/8X+KvvIxQQIrtP0EL+pb9d77WWj9NV2 f/t9n96KH+j5HFTBOcl5/Q2dM0osxRmJhlrMRcWJAJYWSFULAwAA Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Sat, 06 Aug 2011 11:43:18 +0000 (UTC) My Intel DQ67SW (latest BIOS) disables monitor/mwait on the boot CPU if TXT is enabled. We're lucky that the system works at all, since the feature is still enabled on other CPUs. The obvious fix is to just re-enable it ourselves. Signed-off-by: Andy Lutomirski --- arch/x86/kernel/cpu/intel.c | 25 +++++++++++++++++++++++++ 1 files changed, 25 insertions(+), 0 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index c80ab41..5a0150c 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -493,6 +493,31 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); } } + + /* Enable monitor/mwait if BIOS didn't do it for us. */ + if (!cpu_has(c, X86_FEATURE_MWAIT) && cpu_has(c, X86_FEATURE_XMM3) + && c->x86 >= 6 && !(c->x86 == 6 && c->x86_model < 0x1c) + && !(c->x86 == 0xf && c->x86_model < 3)) { + u64 misc_enable; + rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); + misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; + + /* + * Some non-SSE3 cpus will #GP. We check for that, + * but it can't hurt to be safe. + */ + wrmsr_safe(MSR_IA32_MISC_ENABLE, (u32)misc_enable, + (u32)(misc_enable >> 32)); + + /* Re-read monitor capability. */ + if (cpuid_ecx(1) & 0x8) { + set_cpu_cap(c, X86_FEATURE_MWAIT); + + printk(KERN_WARNING FW_WARN "CPU #%d: " + "IA32_MISC_ENABLE.ENABLE_MONITOR_FSM " + "was not set\n", c->cpu_index); + } + } } #ifdef CONFIG_X86_32