From patchwork Thu Oct 31 00:20:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13857333 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2061.outbound.protection.outlook.com [40.107.102.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2CBA7441A; Thu, 31 Oct 2024 00:21:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.102.61 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730334082; cv=fail; b=RDNVeKAwiS5/BfbJxWRuY8fFW/HET78Qr+rBSpTmcXWDPcMfGqY9kXqzRGdQklRS1IyBIhhlGbq6Ts6dexhUXQ1C2gCuxw9WzGaCEgit84CaHgztiI0CAQw2Nt5hu8JolRKz05TXglkGPmcmOc7R9mbtOoD7oDb5jXG0dE1nmg0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730334082; c=relaxed/simple; bh=T8L6FzTN1sBIL9CIAJEAH7FcUZaYLgLcHnf6pgR8qxI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=MrDIkX219aNUS+OR5jIbBt0VyecyZn3z7LXh0RKW4B0J8JScbuoCpvxzxkUyixmj+WnEQ8l7F1TeoPp8US2OnbXovXozXaEke+XCFt05yAUJPs7dFr8PoQm2stJKO0DRxFfQjvcYNobIQhbBrKQm73tNdBitm/wKOWCp2tvfJo4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=dOQNqpyZ; arc=fail smtp.client-ip=40.107.102.61 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="dOQNqpyZ" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=CTU8974aMn81PX2VgHpM0cXNouuePCiU3RGtfbtcOYs32xxI9J/TMfPMHrrgIgD+06lyXkSlQtiumKX1pDyKe3MPFiNfyGSobqCmAJbpR8k5A/AmX8tMbky1Hf4+cMbflf8sDoMwZEq2D6ZivbJs35nnSsfuWen7m7mBpcChcgTeULgTo94Op1kcrspML+KRZ3v57uNfdnK5I/NHi/kW+QJWJjf8hiLmkHVwfLkChOpJxlUYx0iyXfAieGmTZwJWmCEFROLn7dEQnKZtoPVTPAYmLgMqslJltxdvcWWv3aoq82Xe7+oa1Ik1XnVbzL7/TedCWwPy8izXEk8xHAFowg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=a2PmPffYHJLvXuaE01mfAk9vOm8/Ayk+w3Px5GX9drI=; b=PC+bUC4PCK4Gkz8KLztWWX/F8xdKZx5npaW4hZm5IExKt3Qw8srFMLgknB9oxi5+hohd+CN/0GimB0tn7vIlcXyrgB4sfXoMI7wLSVCfnvI7buvvqJGJ7f7th52Q+xgBSakrhvCBVrs3iGTVKOJNGOKtxJg7bA8eBxyllSc1FICGgVr8/AZKPQjUncqu6c4db1xcW4RhYmBKuWRY/dYm+5jg/gkAtBbyxjvt3i7fvBaYg3kcTcXoBNT4wEXsjhVvKmAcUzO8ieeQvFOTkVWG+NjQ/opgt8E3hFpXRbwXReDbnhh6aEFRyFmAAiSClLVyIOegKGAPVvh1O8mtkSjEpQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=a2PmPffYHJLvXuaE01mfAk9vOm8/Ayk+w3Px5GX9drI=; b=dOQNqpyZDkVcIKtOTa/d6dhpAnoyz3vYIFZz6eA9c9Zq+dpu9R3fVsig2JJIVLTWsNUtqQRp/nj2gKW7BRAqbX7gIn7EdL+xveTmTzX2WqEHt074EIgEuKhJ2oVo3VzWK21ZDL3QHC7X1AgyzWySJegexM2N2+g86YxHJlytORkKvfZPb9pHfTXjOgsTvr7T5Dyj9TZLH0tva0lJ5KMC6lXYzQm2cBByxuZGhEhNgj90KcXS+0j4tDfwKrXqixOvWRTszbZdaJ0Qp6xYkYHC/ncKhGtM6m/0Z1oW2PcpU0cbKY28vkWI37xHr52bEM6uQwnr1nlQNEh+pJi4d6tcEQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from CH3PR12MB8659.namprd12.prod.outlook.com (2603:10b6:610:17c::13) by DM4PR12MB7573.namprd12.prod.outlook.com (2603:10b6:8:10f::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.32; Thu, 31 Oct 2024 00:21:02 +0000 Received: from CH3PR12MB8659.namprd12.prod.outlook.com ([fe80::6eb6:7d37:7b4b:1732]) by CH3PR12MB8659.namprd12.prod.outlook.com ([fe80::6eb6:7d37:7b4b:1732%4]) with mapi id 15.20.8093.018; Thu, 31 Oct 2024 00:21:02 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, iommu@lists.linux.dev, Joerg Roedel , Kevin Tian , kvm@vger.kernel.org, Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Lorenzo Pieralisi , "Rafael J. Wysocki" , Robert Moore , Robin Murphy , Sudeep Holla , Will Deacon Cc: Alex Williamson , Donald Dutile , Eric Auger , Hanjun Guo , Jean-Philippe Brucker , Jerry Snitselaar , Moritz Fischer , Michael Shavit , Nicolin Chen , patches@lists.linux.dev, "Rafael J. Wysocki" , Shameerali Kolothum Thodi , Mostafa Saleh Subject: [PATCH v4 07/12] iommu/arm-smmu-v3: Expose the arm_smmu_attach interface Date: Wed, 30 Oct 2024 21:20:51 -0300 Message-ID: <7-v4-9e99b76f3518+3a8-smmuv3_nesting_jgg@nvidia.com> In-Reply-To: <0-v4-9e99b76f3518+3a8-smmuv3_nesting_jgg@nvidia.com> References: X-ClientProxiedBy: BL1P223CA0010.NAMP223.PROD.OUTLOOK.COM (2603:10b6:208:2c4::15) To CH3PR12MB8659.namprd12.prod.outlook.com (2603:10b6:610:17c::13) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PR12MB8659:EE_|DM4PR12MB7573:EE_ X-MS-Office365-Filtering-Correlation-Id: 356e8918-9817-44c1-0aae-08dcf941e4d5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|1800799024|921020; X-Microsoft-Antispam-Message-Info: EdUtHnnjOj4XsU0qXOwUdqnwbzURYClAABOvdWB6h+hj4YCUz34SScp1eVYKFyfOH1D8Jp5M6vxgS541P9aS6QR2v7v7mmqvx4Ypk+9+23X8Xo00ni78HD/RrQk16qAiXy7kcBJAZDaC23qz4oQvbC3NjG9DAHZ5MdvkbU+BjxOOWsAHjOXSQcTh+waXVjawISP6BPN2djxK6pLUwPZxn42RPOeaGKsqnLapnpY2+xcWE8CfNuGnN2GJTPFcVo3LNCze27/SaCVXzQhaW7j2JMRF6wjWihcmmplKA6lHCPrvX+EwhKpiAhZ34/npSkLRA7iT31fHercBtuKKyRneCwinQIySDInqX/9GssK3OfFbGqPT4h92rGryaz8vnf2o9CStPShcCsyD29OgNCSwy/8EY3xtnF4UI0U4x0BTvlPBTQqtH0GteGKXMtulI8F+AVPpPrtBkeAHosFbQJk0f4iI3ENQpW4e0lFm5DzmBtpkQqu/ArRh421reBrrUbDTc84dR6g5Fki6IS72EJdMD/aPGsQWKEeZ2W/LYP+2vuFTKTO6QOq1MYW7F1f01LcVsZEavamt5EnlD7OOhM7hdehA4U8c57Q3D3b3XeXGIw/S6/fsZR7QGapsm0P1RwZEnvFNdQaX/53apWSz98NyB9VBUKs3Tq4BChWgEsNHg21VhOg62deqakQhqk8lj9K8VvUZZBKQFtrM72EduG2vkRU55JEDPmrdq1h0mISAHHp02TPkTn1zyMnIG8hGKbagKtR2IGQLkoF4ey3tmCrlfaJp09mO0P7p0mjn7nSdzCIixz397Xl2EW9mw7LOiDakahDEQxyBT0MBjzZWRGCfGGBlo/EGd0+TvoKDq3jEIb4fr8JLjEaBTEKHXXgPzDjoTNXReyafntSDai4Rei4vEFXuqE9tilcPV3ESWTKnAZTJRp4xAmnP7P5+8KaN1ss2lUqFJgABppe7d6MJrRnGIv3M55xau9WgCOdpIhDbMMAzJVlJCuAhA24f55hIRi8npcGhzrkgv2ZE5N+r7TYOBEPlKrGrfgfQ/dF5c2y94zd/pz7v9TU8EmUuCdE41xq26G3d602RMPZt6lgtjW1VepD4jTKsyZEj9325KtL5J8CZscnl74134etnY5FJgtBEu8NZU3uUwSZaT9GDLk1tpHQHO3g++kUwc1/v6X64dlBNGhBPq+m8XYn20wxD3julEXNo9SFhjPckt2tYnmDYQpf3HbY5YKfB4wHRULuhRCA+jZgi4/VvVysuZGnhsVouU476ByHjWLVPoDedCByRj+2/qDJ+0Yf14i5DCEQxGMcAQ7hpmM5YJ/0vtlBFMoapSCL7zggGfdMjsSB6EjU6vQClgX287dkC/bwwnstdcHQ= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH3PR12MB8659.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(7416014)(366016)(1800799024)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UGLYeOkybmjTrzN26Om4Z2Pr9XhGPnlnNKdtnmTbsNdv9UPxhfgYvlwiorV9ta0w3pFVeCacLoYtCAYfriQl01AWyreaet/7sl1gA1F7NyCKlG7//YckXpC3Vwtm9tnGbauc3SjfTAYdlVGrhEm8qC4jf/oz+xr+WmNVocOWIJVy7byOQdKC7SHSADA4qB1zv+530dezykY5hS9Ihq86iu0RDN/gO+am0gsQfd3dG8lNsPOqiY48MvZ3te5MkcrLmCGAdmxnndwIQfXEYwHjtcL/+IczI51FdPbL0v5cQvwj0glJGwAQqJYCjbDnaC4itiJKHeteK2NPeZsJ31zOZlQ1kIPKaYvkudJ+B1x/FmLkNba4npjhCW/xcjgWrvSeCrdBtRrpzBa4E6q/FkMhzNX8/WvuVga9zgBU9sPGlQcubI3em22Yx0lQ1u0HjBR0AdhLUDllFOMPe5Z1b331nE9ILUOFvhG154e1MMr8e5NXBMVtPb6g7yJP9liT5uABkq4i5TN34rCL4w+SInB+ZPw62ubt3Myby1VDhZnr9s6QRy/3r4iTOYlPuJoyBYJukUeIXs9kJ/cKIif4pcL3X1X4T+8oTeP9M0jgC0rWrnqrErAB/JFhTeCRrpFWW7B3xWpYt0j2D4dNbkP4tOjLlzm46oK6P8OP9XUMH6sROjaeVS2HSvdQ4LjErE2hF2vdDc7uyjIGif9PbcGg3hczDgUfTh3wWqfcPXU1c5eqlGQYe1YNOEcKnFP03ZY+KAelFcxl1Ho0cafbFkmUsE9f5RSbHKykYyIH8DTMw5K0+ZrY+/UIcGNVysImApZownL97C8Q7UPCMMXIBy0SxNnUIc3orB8qeFElyPgRK/9oKfCrASAmYnO3j9O8sJUH9OI8juPshT7/LWmzQh3gMowDVlAvD91NL3nbugKzwtnGrqzTMyC2db/0d0Ydhadf9qXc0QdtG21C2FskzlOdVwfpu5avuDj5uZAqiC0PjXzBum6iJYikyA3A3BrX5TwdLRHE7JX4b3qNb0dpbff/YWEg7f2nTqrXDoY7YdnMwxQqEqKjKHN96jaZTyqsl3kif5P7vppmAgvgIttKU+eDc4NTYPqb50L6o5t2SF08QO4vVW3ebAcmTLiyKlLFutxF3Gjqc3NmEUp2RUfPdfHt37Y3BEXb5cAlAjQGONG9WUv1xT6TQP6KbPFeAjNbt83Yj4ZYxSTBaoH5tpVm4eeiPXBEnDJ2v2JDOMUFK8KEtZ2G961gmcBPXWrrarmygF8dVBqGeR8e0g0GrVKwJFql58Y/9YVtViH3eSgkjZCGRLsDUJZlRJpP6wVOztFazE6wC2Ab9+lSlNT45vVO16Cq40Zdk8wrSRxwSeOwr5ABv9Tgdmy89GQ/oJKmETWVLK01Dcsp5TmchOc3GuUHIrwj8atVVNFRNlDYlvz5lmYsavCbse9eBkJT2/hJJpK2LLNB384UVTCnSGAJ0AxhNQ8eLLyBiG5zPCumk4V7kdFfhGe+2YhvjnEHIH2Dwb+H7IqFSn+6eLMN0u0VefKQxLJcjPK+THQwWYhrRbibgMrF5iNuCAY= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 356e8918-9817-44c1-0aae-08dcf941e4d5 X-MS-Exchange-CrossTenant-AuthSource: CH3PR12MB8659.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2024 00:20:58.8560 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: X7lt88V1vlsIskb2wxyCcg7tu9SBkvSpNbTd1N0Ce0B4bBaEWzJJmA9mD65pufcI X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7573 The arm-smmuv3-iommufd.c file will need to call these functions too. Remove statics and put them in the header file. Remove the kunit visibility protections from arm_smmu_make_abort_ste() and arm_smmu_make_s2_domain_ste(). Reviewed-by: Nicolin Chen Reviewed-by: Kevin Tian Reviewed-by: Jerry Snitselaar Reviewed-by: Mostafa Saleh Reviewed-by: Donald Dutile Tested-by: Nicolin Chen Signed-off-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 22 ++++------------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 27 +++++++++++++++++---- 2 files changed, 27 insertions(+), 22 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 80847fa386fcd2..b4b03206afbf48 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1549,7 +1549,6 @@ static void arm_smmu_write_ste(struct arm_smmu_master *master, u32 sid, } } -VISIBLE_IF_KUNIT void arm_smmu_make_abort_ste(struct arm_smmu_ste *target) { memset(target, 0, sizeof(*target)); @@ -1632,7 +1631,6 @@ void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *target, } EXPORT_SYMBOL_IF_KUNIT(arm_smmu_make_cdtable_ste); -VISIBLE_IF_KUNIT void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, struct arm_smmu_master *master, struct arm_smmu_domain *smmu_domain, @@ -2505,8 +2503,8 @@ arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid) } } -static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master, - const struct arm_smmu_ste *target) +void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master, + const struct arm_smmu_ste *target) { int i, j; struct arm_smmu_device *smmu = master->smmu; @@ -2671,16 +2669,6 @@ static void arm_smmu_remove_master_domain(struct arm_smmu_master *master, spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); } -struct arm_smmu_attach_state { - /* Inputs */ - struct iommu_domain *old_domain; - struct arm_smmu_master *master; - bool cd_needs_ats; - ioasid_t ssid; - /* Resulting state */ - bool ats_enabled; -}; - /* * Start the sequence to attach a domain to a master. The sequence contains three * steps: @@ -2701,8 +2689,8 @@ struct arm_smmu_attach_state { * new_domain can be a non-paging domain. In this case ATS will not be enabled, * and invalidations won't be tracked. */ -static int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, - struct iommu_domain *new_domain) +int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, + struct iommu_domain *new_domain) { struct arm_smmu_master *master = state->master; struct arm_smmu_master_domain *master_domain; @@ -2784,7 +2772,7 @@ static int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, * completes synchronizing the PCI device's ATC and finishes manipulating the * smmu_domain->devices list. */ -static void arm_smmu_attach_commit(struct arm_smmu_attach_state *state) +void arm_smmu_attach_commit(struct arm_smmu_attach_state *state) { struct arm_smmu_master *master = state->master; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 66261fd5bfb2d2..c9e5290e995a64 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -830,21 +830,22 @@ struct arm_smmu_entry_writer_ops { void (*sync)(struct arm_smmu_entry_writer *writer); }; +void arm_smmu_make_abort_ste(struct arm_smmu_ste *target); +void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, + struct arm_smmu_master *master, + struct arm_smmu_domain *smmu_domain, + bool ats_enabled); + #if IS_ENABLED(CONFIG_KUNIT) void arm_smmu_get_ste_used(const __le64 *ent, __le64 *used_bits); void arm_smmu_write_entry(struct arm_smmu_entry_writer *writer, __le64 *cur, const __le64 *target); void arm_smmu_get_cd_used(const __le64 *ent, __le64 *used_bits); -void arm_smmu_make_abort_ste(struct arm_smmu_ste *target); void arm_smmu_make_bypass_ste(struct arm_smmu_device *smmu, struct arm_smmu_ste *target); void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *target, struct arm_smmu_master *master, bool ats_enabled, unsigned int s1dss); -void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, - struct arm_smmu_master *master, - struct arm_smmu_domain *smmu_domain, - bool ats_enabled); void arm_smmu_make_sva_cd(struct arm_smmu_cd *target, struct arm_smmu_master *master, struct mm_struct *mm, u16 asid); @@ -902,6 +903,22 @@ static inline bool arm_smmu_master_canwbs(struct arm_smmu_master *master) IOMMU_FWSPEC_PCI_RC_CANWBS; } +struct arm_smmu_attach_state { + /* Inputs */ + struct iommu_domain *old_domain; + struct arm_smmu_master *master; + bool cd_needs_ats; + ioasid_t ssid; + /* Resulting state */ + bool ats_enabled; +}; + +int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, + struct iommu_domain *new_domain); +void arm_smmu_attach_commit(struct arm_smmu_attach_state *state); +void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master, + const struct arm_smmu_ste *target); + #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); bool arm_smmu_master_sva_supported(struct arm_smmu_master *master);