From patchwork Wed Aug 17 14:03:19 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lutomirski X-Patchwork-Id: 1073982 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p7HE4Dkc028138 for ; Wed, 17 Aug 2011 14:04:13 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753809Ab1HQODv (ORCPT ); Wed, 17 Aug 2011 10:03:51 -0400 Received: from DMZ-MAILSEC-SCANNER-4.MIT.EDU ([18.9.25.15]:50649 "EHLO dmz-mailsec-scanner-4.mit.edu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753790Ab1HQODs (ORCPT ); Wed, 17 Aug 2011 10:03:48 -0400 X-AuditID: 1209190f-b7b44ae000000a24-3e-4e4bc99cebf0 Received: from mailhub-auth-1.mit.edu ( [18.9.21.35]) by dmz-mailsec-scanner-4.mit.edu (Symantec Messaging Gateway) with SMTP id 62.05.02596.C99CB4E4; Wed, 17 Aug 2011 10:01:00 -0400 (EDT) Received: from outgoing.mit.edu (OUTGOING-AUTH.MIT.EDU [18.7.22.103]) by mailhub-auth-1.mit.edu (8.13.8/8.9.2) with ESMTP id p7HE3VXi022752; Wed, 17 Aug 2011 10:03:31 -0400 Received: from localhost (207-172-69-77.c3-0.smr-ubr3.sbo-smr.ma.static.cable.rcn.com [207.172.69.77]) (authenticated bits=0) (User authenticated as luto@ATHENA.MIT.EDU) by outgoing.mit.edu (8.13.6/8.12.4) with ESMTP id p7HE3Th2014305 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES128-SHA bits=128 verify=NOT); Wed, 17 Aug 2011 10:03:30 -0400 (EDT) From: Andy Lutomirski To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: Fenghua Yu , Matthew Garrett , Len Brown , linux-acpi@vger.kernel.org, Ingo Molnar , Andy Lutomirski Subject: [PATCH v4 2/2] x86: Enable monitor/mwait on Intel if BIOS hasn't already Date: Wed, 17 Aug 2011 10:03:19 -0400 Message-Id: X-Mailer: git-send-email 1.7.6 In-Reply-To: References: In-Reply-To: References: X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFIsWRmVeSWpSXmKPExsUixCmqrLvqpLefQddvfYu+K0fZLdqmOVrs fPiWzWL5vn5Gi8u75rBZbLnUzGpx9eFsFosfGx6zOnB43Gr7w+yxc9Zddo/Fe14yeWxa1cnm se7GV3aPz5vkAtiiuGxSUnMyy1KL9O0SuDKe/VnJXPCbu6LpdgdLA+MZzi5GTg4JAROJnpnT mCBsMYkL99azdTFycQgJ7GOUWHbgMjuEs4FR4vzFOawQzjMmiVs7Z4O1sAmoSHQsfQBmiwgY SGxZ+QKsiFngCqPExfk3mEESwgKBEp3nL7KB2CwCqhK3T01hBLF5BYIkdv59BLVbTuLI5edg NifQoM99p9hBbCEBfYllay6w4xKfwCiwgJFhFaNsSm6Vbm5iZk5xarJucXJiXl5qka6JXm5m iV5qSukmRnAQS/LvYPx2UOkQowAHoxIP788eLz8h1sSy4srcQ4ySHExKorx9x7z9hPiS8lMq MxKLM+KLSnNSiw8xSnAwK4nw+hwEyvGmJFZWpRblw6SkOViUxHkbdzj4CQmkJ5akZqemFqQW wWRlODiUJHhVgdEqJFiUmp5akZaZU4KQZuLgBBnOAzQ8HKSGt7ggMbc4Mx0if4pRUUqcVxsk IQCSyCjNg+uFJZlXjOJArwjzyoBU8QATFFz3K6DBTECDb+3yABlckoiQkmpgdN6SVV9qskBA c+bzgvzwT/zpgYw87reX+e88+jWk0vDBz2erBVavmHk5Jf7PbZ6NBfcVnqt/efJm5reO/ZqW DXHrQjq13h477LT8gSRTimSfRdPzozqTbTZOumHEs07i5XPvC09nbVtsuTeFb8PaKyku4oeF Pl3Y8TrUYJLjxAsRkb6/efNzZyuxFGckGmoxFxUnAgBP/aV1DQMAAA== Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Wed, 17 Aug 2011 14:04:13 +0000 (UTC) My Intel DQ67SW (latest BIOS) disables monitor/mwait on the boot CPU if TXT is enabled. We're lucky that the system works at all, since the feature is still enabled on other CPUs. The obvious fix is to just re-enable it ourselves. Signed-off-by: Andy Lutomirski --- arch/x86/kernel/cpu/intel.c | 23 +++++++++++++++++++++++ 1 files changed, 23 insertions(+), 0 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 1f7367d..c79e7b7 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -492,6 +492,29 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); } } + + /* Enable monitor/mwait if BIOS didn't do it for us. */ + if (!cpu_has(c, X86_FEATURE_MWAIT) && cpu_has(c, X86_FEATURE_XMM3) + && c->x86 >= 6 && !(c->x86 == 6 && c->x86_model < 0x1c) + && !(c->x86 == 0xf && c->x86_model < 3)) { + u64 misc_enable; + rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); + misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; + + /* + * Some non-SSE3 cpus will #GP. We check for that, + * but it can't hurt to be safe. + */ + wrmsr_safe(MSR_IA32_MISC_ENABLE, (u32)misc_enable, + (u32)(misc_enable >> 32)); + + /* Re-read monitor capability. */ + if (cpuid_ecx(1) & 0x8) { + set_cpu_cap(c, X86_FEATURE_MWAIT); + + printk(KERN_WARNING FW_WARN "IA32_MISC_ENABLE.ENABLE_MONITOR_FSM was not set\n"); + } + } } #ifdef CONFIG_X86_32