From patchwork Tue Aug 9 12:41:06 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lutomirski X-Patchwork-Id: 1049432 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p79CfiDa021418 for ; Tue, 9 Aug 2011 12:41:44 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753652Ab1HIMla (ORCPT ); Tue, 9 Aug 2011 08:41:30 -0400 Received: from DMZ-MAILSEC-SCANNER-8.MIT.EDU ([18.7.68.37]:61714 "EHLO dmz-mailsec-scanner-8.mit.edu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753587Ab1HIMlU (ORCPT ); Tue, 9 Aug 2011 08:41:20 -0400 X-AuditID: 12074425-b7b15ae000000f71-4e-4e412abf0a9f Received: from mailhub-auth-3.mit.edu ( [18.9.21.43]) by dmz-mailsec-scanner-8.mit.edu (Symantec Messaging Gateway) with SMTP id B9.28.03953.FBA214E4; Tue, 9 Aug 2011 08:40:31 -0400 (EDT) Received: from outgoing.mit.edu (OUTGOING-AUTH.MIT.EDU [18.7.22.103]) by mailhub-auth-3.mit.edu (8.13.8/8.9.2) with ESMTP id p79CfJVL010297; Tue, 9 Aug 2011 08:41:19 -0400 Received: from localhost (207-172-69-77.c3-0.smr-ubr3.sbo-smr.ma.static.cable.rcn.com [207.172.69.77]) (authenticated bits=0) (User authenticated as luto@ATHENA.MIT.EDU) by outgoing.mit.edu (8.13.6/8.12.4) with ESMTP id p79CfIZt001150 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES128-SHA bits=128 verify=NOT); Tue, 9 Aug 2011 08:41:18 -0400 (EDT) From: Andy Lutomirski To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: Fenghua Yu , Matthew Garrett , Len Brown , linux-acpi@vger.kernel.org, Ingo Molnar , Andy Lutomirski Subject: [PATCH v3 2/2] x86: Enable monitor/mwait on Intel if BIOS hasn't already Date: Tue, 9 Aug 2011 08:41:06 -0400 Message-Id: X-Mailer: git-send-email 1.7.6 In-Reply-To: References: In-Reply-To: References: X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrJIsWRmVeSWpSXmKPExsUixCmqrbtfy9HP4N5cA4u+K0fZLdqmOVrs fPiWzWL5vn5Gi8u75rBZbLnUzGpx9eFsFosfGx6zOnB43Gr7w+yxc9Zddo/Fe14yeWxa1cnm se7GV3aPz5vkAtiiuGxSUnMyy1KL9O0SuDJOrrvGXDCfp2LOk2bGBsZHnF2MnBwSAiYSXT92 sEDYYhIX7q1n62Lk4hAS2Mco0T7vG5SznlFi7u5bjBDOUyaJxplzWUFa2ARUJDqWPmACsUUE DCS2rHzBClLELHCFUeLi/BvMIAlhgUCJC9sXgNksAqoSH+/PBWrg4OAVCJJYelceYrWcxJHL z8HmcALNWTN5L1i5kIC+xOFJM1lwiU9gFFjAyLCKUTYlt0o3NzEzpzg1Wbc4OTEvL7VI10Iv N7NELzWldBMjKITZXVR3ME44pHSIUYCDUYmHl5PfwU+INbGsuDL3EKMkB5OSKO8TTUc/Ib6k /JTKjMTijPii0pzU4kOMEhzMSiK86RpAOd6UxMqq1KJ8mJQ0B4uSOO/rHUCTBNITS1KzU1ML UotgsjIcHEoSvBnAWBUSLEpNT61Iy8wpQUgzcXCCDOcBGi4KUsNbXJCYW5yZDpE/xagoJc5r C5IQAElklObB9cJSzCtGcaBXhHmFQap4gOkJrvsV0GAmoMH1dxxABpckIqSkGhjLr6lkmtZF fLX7MnOvso2Tv0rOnpw5QVXz/rxiPm4hbVbZq8Yr80Tyqsq1u1fCag2+n5N6/EtkpoiBRME0 pwdp9hXMgQHJDafMOf7+NpWYuGFNk8bKu5u/qiv+el+qIfJPyU9offADfl5Rx4iIe1tF/3Lx RC+L+qfI0LelKGxD44r5p1gY3iixFGckGmoxFxUnAgDm2w3FDAMAAA== Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Tue, 09 Aug 2011 12:41:44 +0000 (UTC) My Intel DQ67SW (latest BIOS) disables monitor/mwait on the boot CPU if TXT is enabled. We're lucky that the system works at all, since the feature is still enabled on other CPUs. The obvious fix is to just re-enable it ourselves. Signed-off-by: Andy Lutomirski --- arch/x86/kernel/cpu/intel.c | 24 ++++++++++++++++++++++++ 1 files changed, 24 insertions(+), 0 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 7d02873..c49487f 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -492,6 +492,30 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); } } + + /* Enable monitor/mwait if BIOS didn't do it for us. */ + if (!cpu_has(c, X86_FEATURE_MWAIT) && cpu_has(c, X86_FEATURE_XMM3) + && c->x86 >= 6 && !(c->x86 == 6 && c->x86_model < 0x1c) + && !(c->x86 == 0xf && c->x86_model < 3)) { + u64 misc_enable; + rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); + misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; + + /* + * Some non-SSE3 cpus will #GP. We check for that, + * but it can't hurt to be safe. + */ + wrmsr_safe(MSR_IA32_MISC_ENABLE, (u32)misc_enable, + (u32)(misc_enable >> 32)); + + /* Re-read monitor capability. */ + if (cpuid_ecx(1) & 0x8) { + set_cpu_cap(c, X86_FEATURE_MWAIT); + + printk(KERN_WARNING FW_WARN "CPU #%d: IA32_MISC_ENABLE.ENABLE_MONITOR_FSM was not set\n", + c->cpu_index); + } + } } #ifdef CONFIG_X86_32