| Message ID | 20200512211103.530674-1-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | dwmac-meson8b Ethernet RX delay configuration | expand |
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Date: Tue, 12 May 2020 23:10:55 +0200 > The Ethernet TX performance has been historically bad on Meson8b and > Meson8m2 SoCs because high packet loss was seen. I found out that this > was related (yet again) to the RGMII TX delay configuration. > In the process of discussing the big picture (and not just a single > patch) [0] with Andrew I discovered that the IP block behind the > dwmac-meson8b driver actually seems to support the configuration of the > RGMII RX delay (at least on the Meson8b SoC generation). > > Since I sent the first RFC I got additional documentation from Jianxin > (many thanks!). Also I have discovered some more interesting details: > - Meson8b Odroid-C1 requires an RX delay (by either the PHY or the MAC) > Based on the vendor u-boot code (not upstream) I assume that it will > be the same for all Meson8b and Meson8m2 boards > - Khadas VIM2 seems to have the RX delay built into the PCB trace > length. When I enable the RX delay on the PHY or MAC I can't get any > data through. I expect that we will have the same situation on all > GXBB, GXM, AXG, G12A, G12B and SM1 boards. Further clarification is > needed here though (since I can't visually see these lengthened > traces on the PCB). This will be done before sending patches for > these boards. ... Series applied to net-next, thanks Martin.
Hello: This series was applied to khilman/linux-amlogic.git (refs/heads/for-next). On Tue, 12 May 2020 23:10:55 +0200 you wrote: > The Ethernet TX performance has been historically bad on Meson8b and > Meson8m2 SoCs because high packet loss was seen. I found out that this > was related (yet again) to the RGMII TX delay configuration. > In the process of discussing the big picture (and not just a single > patch) [0] with Andrew I discovered that the IP block behind the > dwmac-meson8b driver actually seems to support the configuration of the > RGMII RX delay (at least on the Meson8b SoC generation). > > [...] Here is a summary with links: - [v3,1/8] dt-bindings: net: meson-dwmac: Add the amlogic, rx-delay-ns property https://git.kernel.org/khilman/linux-amlogic/c/7af4c8451d80d0a8622483c27ab141a7c1a94573 - [v3,2/8] dt-bindings: net: dwmac-meson: Document the "timing-adjustment" clock https://git.kernel.org/khilman/linux-amlogic/c/ee0b8e6d02186321be0ea4ec0fb2cbd35bec7e29 - [v3,3/8] net: stmmac: dwmac-meson8b: use FIELD_PREP instead of open-coding it https://git.kernel.org/khilman/linux-amlogic/c/3649abe43251de4357bdd6ef0163de25f96554e9 - [v3,4/8] net: stmmac: dwmac-meson8b: Move the documentation for the TX delay https://git.kernel.org/khilman/linux-amlogic/c/889df20305ffeae0a6bbd435761810ba658e223d - [v3,5/8] net: stmmac: dwmac-meson8b: Add the PRG_ETH0_ADJ_* bits https://git.kernel.org/khilman/linux-amlogic/c/c92d1d2311a0513d8f7f8311f5c2b1d7e78005a0 - [v3,6/8] net: stmmac: dwmac-meson8b: Fetch the "timing-adjustment" clock https://git.kernel.org/khilman/linux-amlogic/c/e4227bff804fc77e2f78c77470d3fbd2d4a6a8d0 - [v3,7/8] net: stmmac: dwmac-meson8b: Make the clock enabling code re-usable https://git.kernel.org/khilman/linux-amlogic/c/a54dc4a4904568fe2c6b2ba249dcc97612affebb - [v3,8/8] net: stmmac: dwmac-meson8b: add support for the RX delay configuration https://git.kernel.org/khilman/linux-amlogic/c/9308c47640d515d16e06a7fdf333c51a39c1b0b1 You are awesome, thank you!
The Ethernet TX performance has been historically bad on Meson8b and Meson8m2 SoCs because high packet loss was seen. I found out that this was related (yet again) to the RGMII TX delay configuration. In the process of discussing the big picture (and not just a single patch) [0] with Andrew I discovered that the IP block behind the dwmac-meson8b driver actually seems to support the configuration of the RGMII RX delay (at least on the Meson8b SoC generation). Since I sent the first RFC I got additional documentation from Jianxin (many thanks!). Also I have discovered some more interesting details: - Meson8b Odroid-C1 requires an RX delay (by either the PHY or the MAC) Based on the vendor u-boot code (not upstream) I assume that it will be the same for all Meson8b and Meson8m2 boards - Khadas VIM2 seems to have the RX delay built into the PCB trace length. When I enable the RX delay on the PHY or MAC I can't get any data through. I expect that we will have the same situation on all GXBB, GXM, AXG, G12A, G12B and SM1 boards. Further clarification is needed here though (since I can't visually see these lengthened traces on the PCB). This will be done before sending patches for these boards. Dependencies for this series: There is a soft dependency for patch #2 on commit f22531438ff42c "dt-bindings: net: dwmac: increase 'maxItems' for 'clocks', 'clock-names' properties" which is currently in Rob's -next tree. That commit is needed to make the dt-bindings schema validation pass for patch #2. That patch has been for ~4 weeks in Robs tree, so I assume that is not going to be dropped. Changes since RFC v2 at [2]: - dropped $ref: /schemas/types.yaml#definitions/uint32 from the "amlogic,rx-delay-ns" in patch #1 ("Don't need to define the type when in standard units." says Rob - thanks, I learned something new). Also use "default: 0" for for this property instead of explaining it in the description text. - added a note to the cover-letter about a hidden dependency for dt-binding schema validation in patch #2 - Added Andrew's Reviewed-by to patches 1-7. Thank you again for the quick and detailed reviews, I appreciate this! - error out if the (optional) timing-adjustment clock is missing but we're asked to enable the RGMII RX delay. The MAC won't work in this specific case and either the RX delay has to be provided by the PHY or the timing-adjustment clock has to be added. - dropped the dts patches (#9-11) which were only added to give an overview how this is going to be used. those will be sent separately - dropped the RFC prefix Changes since RFC v1 at [1]: - add support for the timing adjustment clock input (dt-bindings and in the driver) thanks to the input from the unnamed Ethernet engineer at Amlogic. This is the missing link between the fclk_div2 clock and the Ethernet controller on Meson8b (no traffic would flow if that clock was disabled) - add support fot the amlogic,rx-delay-ns property. The only supported values so far are 0ns and 2ns. The registers seem to allow more precise timing adjustments, but I could not make that work so far. - add more register documentation (for the new RX delay bits) and unified the placement of existing register documentation. Again, thanks to Jianxin and the unnamed Ethernet engineer at Amlogic - DO NOT MERGE: .dts patches to show the conversion of the Meson8b and Meson8m2 boards to "rgmii-id". I didn't have time for all arm64 patches yet, but these will switch to phy-mode = "rgmii-txid" with amlogic,rx-delay-ns = <0> (because the delay seems to be provided by the PCB trace length). [0] https://patchwork.kernel.org/patch/11309891/ [1] https://patchwork.kernel.org/cover/11310719/ [2] https://patchwork.kernel.org/cover/11518257/ Martin Blumenstingl (8): dt-bindings: net: meson-dwmac: Add the amlogic,rx-delay-ns property dt-bindings: net: dwmac-meson: Document the "timing-adjustment" clock net: stmmac: dwmac-meson8b: use FIELD_PREP instead of open-coding it net: stmmac: dwmac-meson8b: Move the documentation for the TX delay net: stmmac: dwmac-meson8b: Add the PRG_ETH0_ADJ_* bits net: stmmac: dwmac-meson8b: Fetch the "timing-adjustment" clock net: stmmac: dwmac-meson8b: Make the clock enabling code re-usable net: stmmac: dwmac-meson8b: add support for the RX delay configuration .../bindings/net/amlogic,meson-dwmac.yaml | 23 ++- .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 146 ++++++++++++++---- 2 files changed, 134 insertions(+), 35 deletions(-)